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[MIPS] Sibyte: Fix interrupt timer off by one bug.

From Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>:

The timers need to be loaded with 1 less than the desired interval not
the interval itself.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle преди 19 години
родител
ревизия
4308cb1628
променени са 1 файла, в които са добавени 2 реда и са изтрити 2 реда
  1. 2 2
      arch/mips/sibyte/sb1250/time.c

+ 2 - 2
arch/mips/sibyte/sb1250/time.c

@@ -75,10 +75,10 @@ void sb1250_time_init(void)
 	/* Disable the timer and set up the count */
 	__raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
 #ifdef CONFIG_SIMULATION
-	__raw_writeq(50000 / HZ,
+	__raw_writeq((50000 / HZ) - 1,
 		     IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
 #else
-	__raw_writeq(1000000 / HZ,
+	__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
 		     IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
 #endif