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@@ -4297,65 +4297,60 @@ static void _print_next_block(int idx, const char *blk)
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pr_cont("%s%s", idx ? ", " : "", blk);
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}
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-static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
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- int par_num, bool print)
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+static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
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+ int *par_num, bool print)
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{
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- int i = 0;
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- u32 cur_bit = 0;
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+ u32 cur_bit;
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+ bool res;
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+ int i;
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+
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+ res = false;
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+
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for (i = 0; sig; i++) {
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- cur_bit = ((u32)0x1 << i);
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+ cur_bit = (0x1UL << i);
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if (sig & cur_bit) {
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- switch (cur_bit) {
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- case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "BRB");
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+ res |= true; /* Each bit is real error! */
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+
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+ if (print) {
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+ switch (cur_bit) {
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+ case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
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+ _print_next_block((*par_num)++, "BRB");
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_print_parity(bp,
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BRB1_REG_BRB1_PRTY_STS);
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- }
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- break;
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- case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "PARSER");
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+ break;
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+ case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
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+ _print_next_block((*par_num)++,
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+ "PARSER");
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_print_parity(bp, PRS_REG_PRS_PRTY_STS);
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- }
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- break;
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- case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "TSDM");
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+ break;
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+ case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
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+ _print_next_block((*par_num)++, "TSDM");
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_print_parity(bp,
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TSDM_REG_TSDM_PRTY_STS);
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- }
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- break;
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- case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++,
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+ break;
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+ case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
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+ _print_next_block((*par_num)++,
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"SEARCHER");
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_print_parity(bp, SRC_REG_SRC_PRTY_STS);
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- }
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- break;
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- case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "TCM");
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- _print_parity(bp,
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- TCM_REG_TCM_PRTY_STS);
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- }
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- break;
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- case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "TSEMI");
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+ break;
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+ case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
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+ _print_next_block((*par_num)++, "TCM");
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+ _print_parity(bp, TCM_REG_TCM_PRTY_STS);
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+ break;
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+ case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
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+ _print_next_block((*par_num)++,
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+ "TSEMI");
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_print_parity(bp,
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TSEM_REG_TSEM_PRTY_STS_0);
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_print_parity(bp,
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TSEM_REG_TSEM_PRTY_STS_1);
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- }
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- break;
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- case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "XPB");
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+ break;
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+ case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
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+ _print_next_block((*par_num)++, "XPB");
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_print_parity(bp, GRCBASE_XPB +
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PB_REG_PB_PRTY_STS);
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+ break;
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}
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- break;
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}
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/* Clear the bit */
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@@ -4363,53 +4358,59 @@ static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
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}
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}
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- return par_num;
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+ return res;
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}
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-static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
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- int par_num, bool *global,
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+static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
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+ int *par_num, bool *global,
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bool print)
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{
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- int i = 0;
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- u32 cur_bit = 0;
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+ u32 cur_bit;
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+ bool res;
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+ int i;
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+
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+ res = false;
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+
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for (i = 0; sig; i++) {
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- cur_bit = ((u32)0x1 << i);
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+ cur_bit = (0x1UL << i);
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if (sig & cur_bit) {
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+ res |= true; /* Each bit is real error! */
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switch (cur_bit) {
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case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "PBF");
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+ _print_next_block((*par_num)++, "PBF");
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_print_parity(bp, PBF_REG_PBF_PRTY_STS);
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}
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break;
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case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "QM");
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+ _print_next_block((*par_num)++, "QM");
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_print_parity(bp, QM_REG_QM_PRTY_STS);
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}
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break;
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case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "TM");
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+ _print_next_block((*par_num)++, "TM");
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_print_parity(bp, TM_REG_TM_PRTY_STS);
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}
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break;
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case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "XSDM");
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+ _print_next_block((*par_num)++, "XSDM");
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_print_parity(bp,
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XSDM_REG_XSDM_PRTY_STS);
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}
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break;
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case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "XCM");
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+ _print_next_block((*par_num)++, "XCM");
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_print_parity(bp, XCM_REG_XCM_PRTY_STS);
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}
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break;
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case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "XSEMI");
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+ _print_next_block((*par_num)++,
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+ "XSEMI");
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_print_parity(bp,
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XSEM_REG_XSEM_PRTY_STS_0);
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_print_parity(bp,
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@@ -4418,7 +4419,7 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
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break;
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case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++,
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+ _print_next_block((*par_num)++,
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"DOORBELLQ");
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_print_parity(bp,
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DORQ_REG_DORQ_PRTY_STS);
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@@ -4426,7 +4427,7 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
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break;
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case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "NIG");
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+ _print_next_block((*par_num)++, "NIG");
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if (CHIP_IS_E1x(bp)) {
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_print_parity(bp,
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NIG_REG_NIG_PRTY_STS);
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@@ -4440,32 +4441,34 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
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break;
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case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
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if (print)
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- _print_next_block(par_num++,
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+ _print_next_block((*par_num)++,
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"VAUX PCI CORE");
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*global = true;
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break;
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case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "DEBUG");
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+ _print_next_block((*par_num)++,
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+ "DEBUG");
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_print_parity(bp, DBG_REG_DBG_PRTY_STS);
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}
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break;
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case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "USDM");
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+ _print_next_block((*par_num)++, "USDM");
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_print_parity(bp,
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USDM_REG_USDM_PRTY_STS);
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}
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break;
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case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "UCM");
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+ _print_next_block((*par_num)++, "UCM");
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_print_parity(bp, UCM_REG_UCM_PRTY_STS);
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}
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break;
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case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "USEMI");
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+ _print_next_block((*par_num)++,
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+ "USEMI");
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_print_parity(bp,
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USEM_REG_USEM_PRTY_STS_0);
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_print_parity(bp,
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@@ -4474,21 +4477,21 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
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break;
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case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "UPB");
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+ _print_next_block((*par_num)++, "UPB");
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_print_parity(bp, GRCBASE_UPB +
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PB_REG_PB_PRTY_STS);
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}
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break;
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case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "CSDM");
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+ _print_next_block((*par_num)++, "CSDM");
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_print_parity(bp,
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CSDM_REG_CSDM_PRTY_STS);
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}
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break;
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case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
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if (print) {
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- _print_next_block(par_num++, "CCM");
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+ _print_next_block((*par_num)++, "CCM");
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_print_parity(bp, CCM_REG_CCM_PRTY_STS);
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}
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break;
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@@ -4499,80 +4502,73 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
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}
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}
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- return par_num;
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+ return res;
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}
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-static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
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- int par_num, bool print)
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+static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
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+ int *par_num, bool print)
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{
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- int i = 0;
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- u32 cur_bit = 0;
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+ u32 cur_bit;
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+ bool res;
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+ int i;
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+
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+ res = false;
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+
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for (i = 0; sig; i++) {
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- cur_bit = ((u32)0x1 << i);
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+ cur_bit = (0x1UL << i);
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if (sig & cur_bit) {
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- switch (cur_bit) {
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- case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "CSEMI");
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+ res |= true; /* Each bit is real error! */
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+ if (print) {
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+ switch (cur_bit) {
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+ case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
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+ _print_next_block((*par_num)++,
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+ "CSEMI");
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_print_parity(bp,
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CSEM_REG_CSEM_PRTY_STS_0);
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_print_parity(bp,
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CSEM_REG_CSEM_PRTY_STS_1);
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- }
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- break;
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- case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "PXP");
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+ break;
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+ case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
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+ _print_next_block((*par_num)++, "PXP");
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_print_parity(bp, PXP_REG_PXP_PRTY_STS);
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_print_parity(bp,
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PXP2_REG_PXP2_PRTY_STS_0);
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_print_parity(bp,
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PXP2_REG_PXP2_PRTY_STS_1);
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- }
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- break;
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- case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
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- if (print)
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- _print_next_block(par_num++,
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- "PXPPCICLOCKCLIENT");
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- break;
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- case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "CFC");
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+ break;
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+ case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
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+ _print_next_block((*par_num)++,
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+ "PXPPCICLOCKCLIENT");
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+ break;
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+ case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
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+ _print_next_block((*par_num)++, "CFC");
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_print_parity(bp,
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CFC_REG_CFC_PRTY_STS);
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- }
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- break;
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- case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "CDU");
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+ break;
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+ case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
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+ _print_next_block((*par_num)++, "CDU");
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_print_parity(bp, CDU_REG_CDU_PRTY_STS);
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- }
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- break;
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- case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "DMAE");
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+ break;
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+ case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
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+ _print_next_block((*par_num)++, "DMAE");
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_print_parity(bp,
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DMAE_REG_DMAE_PRTY_STS);
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- }
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- break;
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- case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "IGU");
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+ break;
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+ case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
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+ _print_next_block((*par_num)++, "IGU");
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if (CHIP_IS_E1x(bp))
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_print_parity(bp,
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HC_REG_HC_PRTY_STS);
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else
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_print_parity(bp,
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IGU_REG_IGU_PRTY_STS);
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- }
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- break;
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- case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
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- if (print) {
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- _print_next_block(par_num++, "MISC");
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+ break;
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+ case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
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+ _print_next_block((*par_num)++, "MISC");
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_print_parity(bp,
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MISC_REG_MISC_PRTY_STS);
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+ break;
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|
|
}
|
|
|
- break;
|
|
|
}
|
|
|
|
|
|
/* Clear the bit */
|
|
@@ -4580,40 +4576,49 @@ static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
|
|
|
}
|
|
|
}
|
|
|
|
|
|
- return par_num;
|
|
|
+ return res;
|
|
|
}
|
|
|
|
|
|
-static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
|
|
|
- bool *global, bool print)
|
|
|
+static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
|
|
|
+ int *par_num, bool *global,
|
|
|
+ bool print)
|
|
|
{
|
|
|
- int i = 0;
|
|
|
- u32 cur_bit = 0;
|
|
|
+ bool res = false;
|
|
|
+ u32 cur_bit;
|
|
|
+ int i;
|
|
|
+
|
|
|
for (i = 0; sig; i++) {
|
|
|
- cur_bit = ((u32)0x1 << i);
|
|
|
+ cur_bit = (0x1UL << i);
|
|
|
if (sig & cur_bit) {
|
|
|
switch (cur_bit) {
|
|
|
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
|
|
|
if (print)
|
|
|
- _print_next_block(par_num++, "MCP ROM");
|
|
|
+ _print_next_block((*par_num)++,
|
|
|
+ "MCP ROM");
|
|
|
*global = true;
|
|
|
+ res |= true;
|
|
|
break;
|
|
|
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
|
|
|
if (print)
|
|
|
- _print_next_block(par_num++,
|
|
|
+ _print_next_block((*par_num)++,
|
|
|
"MCP UMP RX");
|
|
|
*global = true;
|
|
|
+ res |= true;
|
|
|
break;
|
|
|
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
|
|
|
if (print)
|
|
|
- _print_next_block(par_num++,
|
|
|
+ _print_next_block((*par_num)++,
|
|
|
"MCP UMP TX");
|
|
|
*global = true;
|
|
|
+ res |= true;
|
|
|
break;
|
|
|
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
|
|
|
if (print)
|
|
|
- _print_next_block(par_num++,
|
|
|
+ _print_next_block((*par_num)++,
|
|
|
"MCP SCPAD");
|
|
|
- *global = true;
|
|
|
+ /* clear latched SCPAD PATIRY from MCP */
|
|
|
+ REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
|
|
|
+ 1UL << 10);
|
|
|
break;
|
|
|
}
|
|
|
|
|
@@ -4622,45 +4627,50 @@ static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
|
|
|
}
|
|
|
}
|
|
|
|
|
|
- return par_num;
|
|
|
+ return res;
|
|
|
}
|
|
|
|
|
|
-static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
|
|
|
- int par_num, bool print)
|
|
|
+static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
|
|
|
+ int *par_num, bool print)
|
|
|
{
|
|
|
- int i = 0;
|
|
|
- u32 cur_bit = 0;
|
|
|
+ u32 cur_bit;
|
|
|
+ bool res;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ res = false;
|
|
|
+
|
|
|
for (i = 0; sig; i++) {
|
|
|
- cur_bit = ((u32)0x1 << i);
|
|
|
+ cur_bit = (0x1UL << i);
|
|
|
if (sig & cur_bit) {
|
|
|
- switch (cur_bit) {
|
|
|
- case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
|
|
|
- if (print) {
|
|
|
- _print_next_block(par_num++, "PGLUE_B");
|
|
|
+ res |= true; /* Each bit is real error! */
|
|
|
+ if (print) {
|
|
|
+ switch (cur_bit) {
|
|
|
+ case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
|
|
|
+ _print_next_block((*par_num)++,
|
|
|
+ "PGLUE_B");
|
|
|
_print_parity(bp,
|
|
|
- PGLUE_B_REG_PGLUE_B_PRTY_STS);
|
|
|
- }
|
|
|
- break;
|
|
|
- case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
|
|
|
- if (print) {
|
|
|
- _print_next_block(par_num++, "ATC");
|
|
|
+ PGLUE_B_REG_PGLUE_B_PRTY_STS);
|
|
|
+ break;
|
|
|
+ case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
|
|
|
+ _print_next_block((*par_num)++, "ATC");
|
|
|
_print_parity(bp,
|
|
|
ATC_REG_ATC_PRTY_STS);
|
|
|
+ break;
|
|
|
}
|
|
|
- break;
|
|
|
}
|
|
|
-
|
|
|
/* Clear the bit */
|
|
|
sig &= ~cur_bit;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
- return par_num;
|
|
|
+ return res;
|
|
|
}
|
|
|
|
|
|
static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
|
|
|
u32 *sig)
|
|
|
{
|
|
|
+ bool res = false;
|
|
|
+
|
|
|
if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
|
|
|
(sig[1] & HW_PRTY_ASSERT_SET_1) ||
|
|
|
(sig[2] & HW_PRTY_ASSERT_SET_2) ||
|
|
@@ -4677,23 +4687,22 @@ static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
|
|
|
if (print)
|
|
|
netdev_err(bp->dev,
|
|
|
"Parity errors detected in blocks: ");
|
|
|
- par_num = bnx2x_check_blocks_with_parity0(bp,
|
|
|
- sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
|
|
|
- par_num = bnx2x_check_blocks_with_parity1(bp,
|
|
|
- sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
|
|
|
- par_num = bnx2x_check_blocks_with_parity2(bp,
|
|
|
- sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
|
|
|
- par_num = bnx2x_check_blocks_with_parity3(
|
|
|
- sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
|
|
|
- par_num = bnx2x_check_blocks_with_parity4(bp,
|
|
|
- sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
|
|
|
+ res |= bnx2x_check_blocks_with_parity0(bp,
|
|
|
+ sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
|
|
|
+ res |= bnx2x_check_blocks_with_parity1(bp,
|
|
|
+ sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
|
|
|
+ res |= bnx2x_check_blocks_with_parity2(bp,
|
|
|
+ sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
|
|
|
+ res |= bnx2x_check_blocks_with_parity3(bp,
|
|
|
+ sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
|
|
|
+ res |= bnx2x_check_blocks_with_parity4(bp,
|
|
|
+ sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
|
|
|
|
|
|
if (print)
|
|
|
pr_cont("\n");
|
|
|
+ }
|
|
|
|
|
|
- return true;
|
|
|
- } else
|
|
|
- return false;
|
|
|
+ return res;
|
|
|
}
|
|
|
|
|
|
/**
|
|
@@ -7143,7 +7152,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
|
|
|
int port = BP_PORT(bp);
|
|
|
int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
|
|
|
u32 low, high;
|
|
|
- u32 val;
|
|
|
+ u32 val, reg;
|
|
|
|
|
|
DP(NETIF_MSG_HW, "starting port init port %d\n", port);
|
|
|
|
|
@@ -7288,6 +7297,17 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
|
|
|
val |= CHIP_IS_E1(bp) ? 0 : 0x10;
|
|
|
REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
|
|
|
|
|
|
+ /* SCPAD_PARITY should NOT trigger close the gates */
|
|
|
+ reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
|
|
|
+ REG_WR(bp, reg,
|
|
|
+ REG_RD(bp, reg) &
|
|
|
+ ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
|
|
|
+
|
|
|
+ reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
|
|
|
+ REG_WR(bp, reg,
|
|
|
+ REG_RD(bp, reg) &
|
|
|
+ ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
|
|
|
+
|
|
|
bnx2x_init_block(bp, BLOCK_NIG, init_phase);
|
|
|
|
|
|
if (!CHIP_IS_E1x(bp)) {
|