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@@ -48,15 +48,15 @@
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#define PCIE_HOST_INT_STATUS_MASK 0xC3C
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#define PCIE_HOST_INT_STATUS_MASK 0xC3C
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#define PCIE_SCRATCH_2_REG 0xC40
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#define PCIE_SCRATCH_2_REG 0xC40
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#define PCIE_SCRATCH_3_REG 0xC44
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#define PCIE_SCRATCH_3_REG 0xC44
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-#define PCIE_SCRATCH_4_REG 0xCC0
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-#define PCIE_SCRATCH_5_REG 0xCC4
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-#define PCIE_SCRATCH_6_REG 0xCC8
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-#define PCIE_SCRATCH_7_REG 0xCCC
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-#define PCIE_SCRATCH_8_REG 0xCD0
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-#define PCIE_SCRATCH_9_REG 0xCD4
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-#define PCIE_SCRATCH_10_REG 0xCD8
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-#define PCIE_SCRATCH_11_REG 0xCDC
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-#define PCIE_SCRATCH_12_REG 0xCE0
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+#define PCIE_SCRATCH_4_REG 0xCD0
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+#define PCIE_SCRATCH_5_REG 0xCD4
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+#define PCIE_SCRATCH_6_REG 0xCD8
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+#define PCIE_SCRATCH_7_REG 0xCDC
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+#define PCIE_SCRATCH_8_REG 0xCE0
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+#define PCIE_SCRATCH_9_REG 0xCE4
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+#define PCIE_SCRATCH_10_REG 0xCE8
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+#define PCIE_SCRATCH_11_REG 0xCEC
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+#define PCIE_SCRATCH_12_REG 0xCF0
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#define CPU_INTR_DNLD_RDY BIT(0)
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#define CPU_INTR_DNLD_RDY BIT(0)
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#define CPU_INTR_DOOR_BELL BIT(1)
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#define CPU_INTR_DOOR_BELL BIT(1)
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