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@@ -80,6 +80,7 @@
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#define NDSR_RDDREQ (0x1 << 1)
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#define NDSR_WRCMDREQ (0x1)
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+#define NDCB0_LEN_OVRD (0x1 << 28)
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#define NDCB0_ST_ROW_EN (0x1 << 26)
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#define NDCB0_AUTO_RS (0x1 << 25)
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#define NDCB0_CSEL (0x1 << 24)
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@@ -562,6 +563,9 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
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case NAND_CMD_READOOB:
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pxa3xx_set_datasize(info);
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break;
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+ case NAND_CMD_PARAM:
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+ info->use_spare = 0;
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+ break;
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case NAND_CMD_SEQIN:
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exec_cmd = 0;
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break;
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@@ -637,8 +641,10 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
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info->buf_count = 256;
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info->ndcb0 |= NDCB0_CMD_TYPE(0)
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| NDCB0_ADDR_CYC(1)
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+ | NDCB0_LEN_OVRD
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| cmd;
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info->ndcb1 = (column & 0xFF);
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+ info->ndcb3 = 256;
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info->data_size = 256;
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break;
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