|
@@ -1164,11 +1164,7 @@ static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
|
|
|
int idx,
|
|
|
struct nv_adma_prd *aprd)
|
|
|
{
|
|
|
- u8 flags;
|
|
|
-
|
|
|
- memset(aprd, 0, sizeof(struct nv_adma_prd));
|
|
|
-
|
|
|
- flags = 0;
|
|
|
+ u8 flags = 0;
|
|
|
if (qc->tf.flags & ATA_TFLAG_WRITE)
|
|
|
flags |= NV_APRD_WRITE;
|
|
|
if (idx == qc->n_elem - 1)
|
|
@@ -1179,6 +1175,7 @@ static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
|
|
|
aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg)));
|
|
|
aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
|
|
|
aprd->flags = flags;
|
|
|
+ aprd->packet_len = 0;
|
|
|
}
|
|
|
|
|
|
static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
|
|
@@ -1199,6 +1196,8 @@ static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
|
|
|
}
|
|
|
if (idx > 5)
|
|
|
cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
|
|
|
+ else
|
|
|
+ cpb->next_aprd = cpu_to_le64(0);
|
|
|
}
|
|
|
|
|
|
static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
|
|
@@ -1231,7 +1230,10 @@ static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
- memset(cpb, 0, sizeof(struct nv_adma_cpb));
|
|
|
+ cpb->resp_flags = NV_CPB_RESP_DONE;
|
|
|
+ wmb();
|
|
|
+ cpb->ctl_flags = 0;
|
|
|
+ wmb();
|
|
|
|
|
|
cpb->len = 3;
|
|
|
cpb->tag = qc->tag;
|
|
@@ -1255,6 +1257,8 @@ static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
|
|
|
finished filling in all of the contents */
|
|
|
wmb();
|
|
|
cpb->ctl_flags = ctl_flags;
|
|
|
+ wmb();
|
|
|
+ cpb->resp_flags = 0;
|
|
|
}
|
|
|
|
|
|
static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
|