|
@@ -13115,7 +13115,7 @@ static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
|
|
|
return 512;
|
|
|
}
|
|
|
|
|
|
-DEFINE_PCI_DEVICE_TABLE(write_reorder_chipsets) = {
|
|
|
+static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
|
|
@@ -13469,7 +13469,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
|
|
|
* every mailbox register write to force the writes to be
|
|
|
* posted to the chip in order.
|
|
|
*/
|
|
|
- if (pci_dev_present(write_reorder_chipsets) &&
|
|
|
+ if (pci_dev_present(tg3_write_reorder_chipsets) &&
|
|
|
!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
|
|
|
tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
|
|
|
|
|
@@ -14225,7 +14225,7 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
|
|
|
|
|
|
#define TEST_BUFFER_SIZE 0x2000
|
|
|
|
|
|
-DEFINE_PCI_DEVICE_TABLE(dma_wait_state_chipsets) = {
|
|
|
+static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
|
|
|
{ },
|
|
|
};
|
|
@@ -14404,7 +14404,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
|
|
|
* now look for chipsets that are known to expose the
|
|
|
* DMA bug without failing the test.
|
|
|
*/
|
|
|
- if (pci_dev_present(dma_wait_state_chipsets)) {
|
|
|
+ if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
|
|
|
tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
|
|
|
tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
|
|
|
} else {
|