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@@ -55,6 +55,9 @@
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/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
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#define SWRST SICA_SWRST
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#define SYSCR SICA_SYSCR
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+#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
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+#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
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+#define RESET_SOFTWARE (SWRST_OCCURRED)
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/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
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#define SICA_SWRST 0xFFC00100 /* Software Reset register */
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Mike Frysinger