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@@ -4564,13 +4564,13 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
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ri = &tpr->rx_std_buffers[desc_idx];
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dma_addr = pci_unmap_addr(ri, mapping);
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skb = ri->skb;
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- post_ptr = &tpr->rx_std_ptr;
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+ post_ptr = &tpr->rx_std_prod_idx;
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rx_std_posted++;
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} else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
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ri = &tpr->rx_jmb_buffers[desc_idx];
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dma_addr = pci_unmap_addr(ri, mapping);
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skb = ri->skb;
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- post_ptr = &tpr->rx_jmb_ptr;
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+ post_ptr = &tpr->rx_jmb_prod_idx;
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} else
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goto next_pkt_nopost;
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@@ -4687,12 +4687,12 @@ next_pkt_nopost:
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/* Refill RX ring(s). */
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if (work_mask & RXD_OPAQUE_RING_STD) {
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- sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
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+ sw_idx = tpr->rx_std_prod_idx % TG3_RX_RING_SIZE;
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tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
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sw_idx);
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}
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if (work_mask & RXD_OPAQUE_RING_JUMBO) {
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- sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
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+ sw_idx = tpr->rx_jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
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tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
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sw_idx);
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}
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@@ -7509,14 +7509,14 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
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- tpr->rx_std_ptr = tp->rx_pending;
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+ tpr->rx_std_prod_idx = tp->rx_pending;
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tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
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- tpr->rx_std_ptr);
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+ tpr->rx_std_prod_idx);
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- tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
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+ tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
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tp->rx_jumbo_pending : 0;
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tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
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- tpr->rx_jmb_ptr);
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+ tpr->rx_jmb_prod_idx);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
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tw32(STD_REPLENISH_LWM, 32);
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