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+/*
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+ * Copyright (C) 2008 Michal Simek
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+ * Copyright (C) 2008 PetaLogix
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+ * Copyright (C) 2006 Atmark Techno, Inc.
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+ *
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ */
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+
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+#ifndef _ASM_MICROBLAZE_REGISTERS_H
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+#define _ASM_MICROBLAZE_REGISTERS_H
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+
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+#define MSR_BE (1<<0) /* 0x001 */
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+#define MSR_IE (1<<1) /* 0x002 */
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+#define MSR_C (1<<2) /* 0x004 */
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+#define MSR_BIP (1<<3) /* 0x008 */
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+#define MSR_FSL (1<<4) /* 0x010 */
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+#define MSR_ICE (1<<5) /* 0x020 */
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+#define MSR_DZ (1<<6) /* 0x040 */
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+#define MSR_DCE (1<<7) /* 0x080 */
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+#define MSR_EE (1<<8) /* 0x100 */
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+#define MSR_EIP (1<<9) /* 0x200 */
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+#define MSR_CC (1<<31)
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+
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+/* Floating Point Status Register (FSR) Bits */
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+#define FSR_IO (1<<4) /* Invalid operation */
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+#define FSR_DZ (1<<3) /* Divide-by-zero */
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+#define FSR_OF (1<<2) /* Overflow */
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+#define FSR_UF (1<<1) /* Underflow */
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+#define FSR_DO (1<<0) /* Denormalized operand error */
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+
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+#endif /* _ASM_MICROBLAZE_REGISTERS_H */
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