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@@ -2882,7 +2882,7 @@ struct cxsr_latency {
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unsigned long cursor_hpll_disable;
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};
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-static struct cxsr_latency cxsr_latency_table[] = {
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+static const struct cxsr_latency cxsr_latency_table[] = {
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{1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
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{1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
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{1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
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@@ -2920,11 +2920,13 @@ static struct cxsr_latency cxsr_latency_table[] = {
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{0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
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};
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-static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
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- int fsb, int mem)
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+static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
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+ int is_ddr3,
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+ int fsb,
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+ int mem)
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{
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+ const struct cxsr_latency *latency;
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int i;
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- struct cxsr_latency *latency;
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if (fsb == 0 || mem == 0)
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return NULL;
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@@ -3035,12 +3037,12 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
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int pixel_size)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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+ const struct cxsr_latency *latency;
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u32 reg;
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unsigned long wm;
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- struct cxsr_latency *latency;
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int sr_clock;
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- latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
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+ latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
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dev_priv->fsb_freq, dev_priv->mem_freq);
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if (!latency) {
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DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
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