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@@ -905,22 +905,18 @@ u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
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static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
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{
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- int rc;
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+ int ret;
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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- rc = iwl_grab_nic_access(priv);
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- if (rc) {
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+ ret = iwl_grab_nic_access(priv);
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+ if (ret) {
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spin_unlock_irqrestore(&priv->lock, flags);
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- return rc;
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+ return ret;
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}
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if (src == IWL_PWR_SRC_VAUX) {
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- u32 val;
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-
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- rc = pci_read_config_dword(priv->pci_dev,
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- PCI_POWER_SOURCE, &val);
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- if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
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+ if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
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iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
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~APMG_PS_CTRL_MSK_PWR_SRC);
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@@ -929,8 +925,9 @@ static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
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iwl_poll_bit(priv, CSR_GPIO_IN,
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CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
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CSR_GPIO_IN_BIT_AUX_POWER, 5000);
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- } else
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+ } else {
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iwl_release_nic_access(priv);
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+ }
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} else {
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iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
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@@ -942,7 +939,7 @@ static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
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}
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spin_unlock_irqrestore(&priv->lock, flags);
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- return rc;
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+ return ret;
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}
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static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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