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@@ -87,6 +87,15 @@ static inline void ssbi_writel(struct msm_ssbi *ssbi, u32 val, u32 reg)
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writel(val, ssbi->base + reg);
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}
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+/*
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+ * Via private exchange with one of the original authors, the hardware
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+ * should generally finish a transaction in about 5us. The worst
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+ * case, is when using the arbiter and both other CPUs have just
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+ * started trying to use the SSBI bus will result in a time of about
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+ * 20us. It should never take longer than this.
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+ *
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+ * As such, this wait merely spins, with a udelay.
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+ */
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static int ssbi_wait_mask(struct msm_ssbi *ssbi, u32 set_mask, u32 clr_mask)
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{
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u32 timeout = SSBI_TIMEOUT_US;
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@@ -161,6 +170,10 @@ err:
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return ret;
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}
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+/*
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+ * See ssbi_wait_mask for an explanation of the time and the
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+ * busywait.
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+ */
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static inline int
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msm_ssbi_pa_transfer(struct msm_ssbi *ssbi, u32 cmd, u8 *data)
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{
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