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@@ -100,11 +100,36 @@ ENTRY(cpu_v7_switch_mm)
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* - pte - PTE value to store
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* - ext - value for extended PTE bits
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*/
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- armv6_mt_table cpu_v7
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-
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ENTRY(cpu_v7_set_pte_ext)
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#ifdef CONFIG_MMU
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- armv6_set_pte_ext cpu_v7
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+ str r1, [r0], #-2048 @ linux version
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+
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+ bic r3, r1, #0x000003f0
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+ bic r3, r3, #PTE_TYPE_MASK
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+ orr r3, r3, r2
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+ orr r3, r3, #PTE_EXT_AP0 | 2
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+
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+ tst r2, #1 << 4
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+ orrne r3, r3, #PTE_EXT_TEX(1)
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+
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+ tst r1, #L_PTE_WRITE
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+ tstne r1, #L_PTE_DIRTY
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+ orreq r3, r3, #PTE_EXT_APX
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+
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+ tst r1, #L_PTE_USER
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+ orrne r3, r3, #PTE_EXT_AP1
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+ tstne r3, #PTE_EXT_APX
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+ bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
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+
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+ tst r1, #L_PTE_EXEC
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+ orreq r3, r3, #PTE_EXT_XN
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+
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+ tst r1, #L_PTE_YOUNG
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+ tstne r1, #L_PTE_PRESENT
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+ moveq r3, #0
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+
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+ str r3, [r0]
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+ mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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#endif
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mov pc, lr
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@@ -148,6 +173,10 @@ __v7_setup:
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mov r10, #0x1f @ domains 0, 1 = manager
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mcr p15, 0, r10, c3, c0, 0 @ load domain access register
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#endif
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+ ldr r5, =0x40e040e0
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+ ldr r6, =0xff0aa1a8
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+ mcr p15, 0, r5, c10, c2, 0 @ write PRRR
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+ mcr p15, 0, r6, c10, c2, 1 @ write NMRR
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adr r5, v7_crval
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ldmia r5, {r5, r6}
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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@@ -163,7 +192,7 @@ __v7_setup:
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*/
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.type v7_crval, #object
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v7_crval:
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- crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c
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+ crval clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c
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__v7_setup_stack:
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.space 4 * 11 @ 11 registers
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