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@@ -126,9 +126,8 @@ static void isp1760_writel(const unsigned int val, __u32 __iomem *regs)
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* doesn't quite work because some people have to enforce 32-bit access
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*/
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static void priv_read_copy(struct isp1760_hcd *priv, u32 *src,
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- __u32 __iomem *dst, u32 offset, u32 len)
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+ __u32 __iomem *dst, u32 len)
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{
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- struct usb_hcd *hcd = priv_to_hcd(priv);
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u32 val;
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u8 *buff8;
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@@ -136,11 +135,6 @@ static void priv_read_copy(struct isp1760_hcd *priv, u32 *src,
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printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len);
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return;
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}
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- isp1760_writel(offset, hcd->regs + HC_MEMORY_REG);
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- /* XXX
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- * 90nsec delay, the spec says something how this could be avoided.
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- */
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- mdelay(1);
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while (len >= 4) {
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*src = __raw_readl(dst);
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@@ -987,8 +981,20 @@ static void do_atl_int(struct usb_hcd *usb_hcd)
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printk(KERN_ERR "qh is 0\n");
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continue;
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}
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- priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs,
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- atl_regs, sizeof(ptd));
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+ isp1760_writel(atl_regs + ISP_BANK(0), usb_hcd->regs +
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+ HC_MEMORY_REG);
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+ isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
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+ HC_MEMORY_REG);
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+ /*
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+ * write bank1 address twice to ensure the 90ns delay (time
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+ * between BANK0 write and the priv_read_copy() call is at
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+ * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns)
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+ */
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+ isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
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+ HC_MEMORY_REG);
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+
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+ priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs +
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+ ISP_BANK(0), sizeof(ptd));
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dw1 = le32_to_cpu(ptd.dw1);
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dw2 = le32_to_cpu(ptd.dw2);
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@@ -1091,7 +1097,7 @@ static void do_atl_int(struct usb_hcd *usb_hcd)
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case IN_PID:
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priv_read_copy(priv,
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priv->atl_ints[queue_entry].data_buffer,
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- usb_hcd->regs + payload, payload,
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+ usb_hcd->regs + payload + ISP_BANK(1),
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length);
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case OUT_PID:
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@@ -1206,8 +1212,20 @@ static void do_intl_int(struct usb_hcd *usb_hcd)
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continue;
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}
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- priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs,
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- int_regs, sizeof(ptd));
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+ isp1760_writel(int_regs + ISP_BANK(0), usb_hcd->regs +
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+ HC_MEMORY_REG);
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+ isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
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+ HC_MEMORY_REG);
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+ /*
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+ * write bank1 address twice to ensure the 90ns delay (time
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+ * between BANK0 write and the priv_read_copy() call is at
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+ * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns)
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+ */
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+ isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
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+ HC_MEMORY_REG);
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+
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+ priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs +
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+ ISP_BANK(0), sizeof(ptd));
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dw1 = le32_to_cpu(ptd.dw1);
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dw3 = le32_to_cpu(ptd.dw3);
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check_int_err_status(le32_to_cpu(ptd.dw4));
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@@ -1242,7 +1260,7 @@ static void do_intl_int(struct usb_hcd *usb_hcd)
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case IN_PID:
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priv_read_copy(priv,
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priv->int_ints[queue_entry].data_buffer,
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- usb_hcd->regs + payload , payload,
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+ usb_hcd->regs + payload + ISP_BANK(1),
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length);
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case OUT_PID:
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