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@@ -60,6 +60,19 @@
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clock-frequency = <24000000>;
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};
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+ ref25: ref25M {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <25000000>;
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+ };
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+
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+ pllb: pllb {
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+ #clock-cells = <0>;
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+ compatible = "via,vt8500-pll-clock";
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+ clocks = <&ref25>;
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+ reg = <0x204>;
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+ };
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+
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clkuart0: uart0 {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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@@ -107,6 +120,16 @@
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enable-reg = <0x250>;
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enable-bit = <23>;
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};
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+
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+ clksdhc: sdhc {
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+ #clock-cells = <0>;
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+ compatible = "via,vt8500-device-clock";
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+ clocks = <&pllb>;
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+ divisor-reg = <0x328>;
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+ divisor-mask = <0x3f>;
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+ enable-reg = <0x254>;
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+ enable-bit = <18>;
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+ };
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};
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};
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@@ -187,5 +210,13 @@
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reg = <0xd8100000 0x10000>;
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interrupts = <48>;
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};
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+
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+ sdhc@d800a000 {
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+ compatible = "wm,wm8505-sdhc";
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+ reg = <0xd800a000 0x1000>;
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+ interrupts = <20 21>;
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+ clocks = <&clksdhc>;
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+ bus-width = <4>;
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+ };
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};
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};
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