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@@ -11,7 +11,7 @@
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* 2 of the License, or (at your option) any later version.
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*/
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-#undef DEBUG
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+#define DEBUG
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#include <linux/kernel.h>
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#include <linux/pci.h>
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@@ -22,6 +22,7 @@
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#include <linux/list.h>
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#include <linux/syscalls.h>
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#include <linux/irq.h>
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+#include <linux/vmalloc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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@@ -41,35 +42,26 @@
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unsigned long pci_probe_only = 1;
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int pci_assign_all_buses = 0;
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-static int pci_initial_scan_done;
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static void fixup_resource(struct resource *res, struct pci_dev *dev);
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static void do_bus_setup(struct pci_bus *bus);
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-static void phbs_remap_io(void);
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/* pci_io_base -- the base address from which io bars are offsets.
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* This is the lowest I/O base address (so bar values are always positive),
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* and it *must* be the start of ISA space if an ISA bus exists because
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- * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
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- * page is mapped and isa_io_limit prevents access to it.
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+ * ISA drivers use hard coded offsets. If no ISA bus exists nothing
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+ * is mapped on the first 64K of IO space
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*/
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-unsigned long isa_io_base; /* NULL if no ISA bus */
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-EXPORT_SYMBOL(isa_io_base);
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-unsigned long pci_io_base;
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+unsigned long pci_io_base = ISA_IO_BASE;
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EXPORT_SYMBOL(pci_io_base);
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-void iSeries_pcibios_init(void);
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-
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LIST_HEAD(hose_list);
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static struct dma_mapping_ops *pci_dma_ops;
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+/* XXX kill that some day ... */
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int global_phb_number; /* Global phb counter */
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-/* Cached ISA bridge dev. */
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-struct pci_dev *ppc64_isabridge_dev = NULL;
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-EXPORT_SYMBOL_GPL(ppc64_isabridge_dev);
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-
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void set_pci_dma_ops(struct dma_mapping_ops *dma_ops)
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{
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pci_dma_ops = dma_ops;
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@@ -100,7 +92,7 @@ void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region
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return;
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if (res->flags & IORESOURCE_IO)
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- offset = (unsigned long)hose->io_base_virt - pci_io_base;
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+ offset = (unsigned long)hose->io_base_virt - _IO_BASE;
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if (res->flags & IORESOURCE_MEM)
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offset = hose->pci_mem_offset;
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@@ -119,7 +111,7 @@ void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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return;
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if (res->flags & IORESOURCE_IO)
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- offset = (unsigned long)hose->io_base_virt - pci_io_base;
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+ offset = (unsigned long)hose->io_base_virt - _IO_BASE;
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if (res->flags & IORESOURCE_MEM)
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offset = hose->pci_mem_offset;
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@@ -156,7 +148,7 @@ void pcibios_align_resource(void *data, struct resource *res,
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if (res->flags & IORESOURCE_IO) {
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unsigned long offset = (unsigned long)hose->io_base_virt -
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- pci_io_base;
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+ _IO_BASE;
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/* Make sure we start at our min on all hoses */
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if (start - offset < PCIBIOS_MIN_IO)
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start = PCIBIOS_MIN_IO + offset;
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@@ -535,10 +527,16 @@ void __devinit scan_phb(struct pci_controller *hose)
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bus->secondary = hose->first_busno;
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hose->bus = bus;
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+ if (!firmware_has_feature(FW_FEATURE_ISERIES))
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+ pcibios_map_io_space(bus);
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+
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bus->resource[0] = res = &hose->io_resource;
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- if (res->flags && request_resource(&ioport_resource, res))
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+ if (res->flags && request_resource(&ioport_resource, res)) {
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printk(KERN_ERR "Failed to request PCI IO region "
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"on PCI domain %04x\n", hose->global_number);
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+ DBG("res->start = 0x%016lx, res->end = 0x%016lx\n",
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+ res->start, res->end);
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+ }
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for (i = 0; i < 3; ++i) {
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res = &hose->mem_resources[i];
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@@ -596,17 +594,6 @@ static int __init pcibios_init(void)
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if (ppc_md.pcibios_fixup)
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ppc_md.pcibios_fixup();
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- /* Cache the location of the ISA bridge (if we have one) */
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- ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
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- if (ppc64_isabridge_dev != NULL)
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- printk(KERN_DEBUG "ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
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-
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- if (!firmware_has_feature(FW_FEATURE_ISERIES))
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- /* map in PCI I/O space */
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- phbs_remap_io();
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-
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- pci_initial_scan_done = 1;
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-
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printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
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return 0;
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@@ -711,7 +698,7 @@ static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
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#endif
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res_bit = IORESOURCE_MEM;
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} else {
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- io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
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+ io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
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*offset += io_offset;
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res_bit = IORESOURCE_IO;
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}
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@@ -881,76 +868,6 @@ void pcibios_add_platform_entries(struct pci_dev *pdev)
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device_create_file(&pdev->dev, &dev_attr_devspec);
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}
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-#define ISA_SPACE_MASK 0x1
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-#define ISA_SPACE_IO 0x1
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-
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-static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
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- unsigned long phb_io_base_phys,
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- void __iomem * phb_io_base_virt)
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-{
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- /* Remove these asap */
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-
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- struct pci_address {
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- u32 a_hi;
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- u32 a_mid;
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- u32 a_lo;
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- };
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-
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- struct isa_address {
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- u32 a_hi;
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- u32 a_lo;
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- };
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-
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- struct isa_range {
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- struct isa_address isa_addr;
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- struct pci_address pci_addr;
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- unsigned int size;
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- };
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-
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- const struct isa_range *range;
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- unsigned long pci_addr;
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- unsigned int isa_addr;
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- unsigned int size;
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- int rlen = 0;
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-
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- range = of_get_property(isa_node, "ranges", &rlen);
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- if (range == NULL || (rlen < sizeof(struct isa_range))) {
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- printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
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- "mapping 64k\n");
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- __ioremap_explicit(phb_io_base_phys,
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- (unsigned long)phb_io_base_virt,
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- 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
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- return;
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- }
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-
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- /* From "ISA Binding to 1275"
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- * The ranges property is laid out as an array of elements,
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- * each of which comprises:
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- * cells 0 - 1: an ISA address
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- * cells 2 - 4: a PCI address
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- * (size depending on dev->n_addr_cells)
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- * cell 5: the size of the range
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- */
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- if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
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- isa_addr = range->isa_addr.a_lo;
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- pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
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- range->pci_addr.a_lo;
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-
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- /* Assume these are both zero */
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- if ((pci_addr != 0) || (isa_addr != 0)) {
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- printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
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- __FUNCTION__);
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- return;
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- }
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-
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- size = PAGE_ALIGN(range->size);
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-
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- __ioremap_explicit(phb_io_base_phys,
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- (unsigned long) phb_io_base_virt,
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- size, _PAGE_NO_CACHE | _PAGE_GUARDED);
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- }
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-}
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-
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void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
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struct device_node *dev, int prim)
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{
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@@ -1045,155 +962,122 @@ void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
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}
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}
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-void __devinit pci_setup_phb_io(struct pci_controller *hose, int primary)
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+#ifdef CONFIG_HOTPLUG
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+
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+int pcibios_unmap_io_space(struct pci_bus *bus)
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{
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- unsigned long size = hose->pci_io_size;
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- unsigned long io_virt_offset;
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- struct resource *res;
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- struct device_node *isa_dn;
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+ struct pci_controller *hose;
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- if (size == 0)
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- return;
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+ WARN_ON(bus == NULL);
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- hose->io_base_virt = reserve_phb_iospace(size);
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- DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
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- hose->global_number, hose->io_base_phys,
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- (unsigned long) hose->io_base_virt);
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-
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- if (primary) {
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- pci_io_base = (unsigned long)hose->io_base_virt;
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- isa_dn = of_find_node_by_type(NULL, "isa");
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- if (isa_dn) {
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- isa_io_base = pci_io_base;
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- pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
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- hose->io_base_virt);
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- of_node_put(isa_dn);
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- }
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- }
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+ /* If this is not a PHB, we only flush the hash table over
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+ * the area mapped by this bridge. We don't play with the PTE
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+ * mappings since we might have to deal with sub-page alignemnts
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+ * so flushing the hash table is the only sane way to make sure
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+ * that no hash entries are covering that removed bridge area
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+ * while still allowing other busses overlapping those pages
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+ */
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+ if (bus->self) {
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+ struct resource *res = bus->resource[0];
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- io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
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- res = &hose->io_resource;
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- res->start += io_virt_offset;
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- res->end += io_virt_offset;
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+ DBG("IO unmapping for PCI-PCI bridge %s\n",
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+ pci_name(bus->self));
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- /* If this is called after the initial PCI scan, then we need to
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- * proceed to IO mappings now
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- */
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- if (pci_initial_scan_done)
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- __ioremap_explicit(hose->io_base_phys,
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- (unsigned long)hose->io_base_virt,
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- hose->pci_io_size,
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- _PAGE_NO_CACHE | _PAGE_GUARDED);
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-}
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+ __flush_hash_table_range(&init_mm, res->start + _IO_BASE,
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+ res->end - res->start + 1);
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+ return 0;
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+ }
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-void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
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- int primary)
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-{
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- unsigned long size = hose->pci_io_size;
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- unsigned long io_virt_offset;
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- struct resource *res;
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+ /* Get the host bridge */
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+ hose = pci_bus_to_host(bus);
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- if (size == 0)
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- return;
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+ /* Check if we have IOs allocated */
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+ if (hose->io_base_alloc == 0)
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+ return 0;
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- hose->io_base_virt = __ioremap(hose->io_base_phys, size,
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- _PAGE_NO_CACHE | _PAGE_GUARDED);
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- DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
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- hose->global_number, hose->io_base_phys,
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- (unsigned long) hose->io_base_virt);
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+ DBG("IO unmapping for PHB %s\n",
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+ ((struct device_node *)hose->arch_data)->full_name);
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+ DBG(" alloc=0x%p\n", hose->io_base_alloc);
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- if (primary)
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- pci_io_base = (unsigned long)hose->io_base_virt;
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+ /* This is a PHB, we fully unmap the IO area */
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+ vunmap(hose->io_base_alloc);
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- io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
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- res = &hose->io_resource;
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- res->start += io_virt_offset;
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- res->end += io_virt_offset;
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+ return 0;
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}
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+EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
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+#endif /* CONFIG_HOTPLUG */
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-static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
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- unsigned long *start_virt, unsigned long *size)
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+int __devinit pcibios_map_io_space(struct pci_bus *bus)
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{
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- struct pci_controller *hose = pci_bus_to_host(bus);
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- struct resource *res;
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-
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- if (bus->self)
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- res = bus->resource[0];
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- else
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- /* Root Bus */
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- res = &hose->io_resource;
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-
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- if (res->end == 0 && res->start == 0)
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- return 1;
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+ struct vm_struct *area;
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+ unsigned long phys_page;
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+ unsigned long size_page;
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+ unsigned long io_virt_offset;
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+ struct pci_controller *hose;
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- *start_virt = pci_io_base + res->start;
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- *start_phys = *start_virt + hose->io_base_phys
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- - (unsigned long) hose->io_base_virt;
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+ WARN_ON(bus == NULL);
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- if (res->end > res->start)
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- *size = res->end - res->start + 1;
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- else {
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- printk("%s(): unexpected region 0x%lx->0x%lx\n",
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- __FUNCTION__, res->start, res->end);
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- return 1;
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+ /* If this not a PHB, nothing to do, page tables still exist and
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+ * thus HPTEs will be faulted in when needed
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+ */
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+ if (bus->self) {
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+ DBG("IO mapping for PCI-PCI bridge %s\n",
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+ pci_name(bus->self));
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+ DBG(" virt=0x%016lx...0x%016lx\n",
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+ bus->resource[0]->start + _IO_BASE,
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+ bus->resource[0]->end + _IO_BASE);
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+ return 0;
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}
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- return 0;
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-}
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-
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-int unmap_bus_range(struct pci_bus *bus)
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-{
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- unsigned long start_phys;
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- unsigned long start_virt;
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- unsigned long size;
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-
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- if (!bus) {
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- printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
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- return 1;
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- }
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-
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- if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
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- return 1;
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- if (__iounmap_explicit((void __iomem *) start_virt, size))
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- return 1;
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+ /* Get the host bridge */
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+ hose = pci_bus_to_host(bus);
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+ phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
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+ size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
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- return 0;
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-}
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-EXPORT_SYMBOL(unmap_bus_range);
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+ /* Make sure IO area address is clear */
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+ hose->io_base_alloc = NULL;
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-int remap_bus_range(struct pci_bus *bus)
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-{
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- unsigned long start_phys;
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- unsigned long start_virt;
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- unsigned long size;
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+ /* If there's no IO to map on that bus, get away too */
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+ if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
|
|
|
+ return 0;
|
|
|
|
|
|
- if (!bus) {
|
|
|
- printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
|
|
|
- return 1;
|
|
|
- }
|
|
|
-
|
|
|
-
|
|
|
- if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
|
|
|
- return 1;
|
|
|
- if (start_phys == 0)
|
|
|
- return 1;
|
|
|
- printk(KERN_DEBUG "mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
|
|
|
- if (__ioremap_explicit(start_phys, start_virt, size,
|
|
|
- _PAGE_NO_CACHE | _PAGE_GUARDED))
|
|
|
- return 1;
|
|
|
+ /* Let's allocate some IO space for that guy. We don't pass
|
|
|
+ * VM_IOREMAP because we don't care about alignment tricks that
|
|
|
+ * the core does in that case. Maybe we should due to stupid card
|
|
|
+ * with incomplete address decoding but I'd rather not deal with
|
|
|
+ * those outside of the reserved 64K legacy region.
|
|
|
+ */
|
|
|
+ area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
|
|
|
+ if (area == NULL)
|
|
|
+ return -ENOMEM;
|
|
|
+ hose->io_base_alloc = area->addr;
|
|
|
+ hose->io_base_virt = (void __iomem *)(area->addr +
|
|
|
+ hose->io_base_phys - phys_page);
|
|
|
+
|
|
|
+ DBG("IO mapping for PHB %s\n",
|
|
|
+ ((struct device_node *)hose->arch_data)->full_name);
|
|
|
+ DBG(" phys=0x%016lx, virt=0x%p (alloc=0x%p)\n",
|
|
|
+ hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
|
|
|
+ DBG(" size=0x%016lx (alloc=0x%016lx)\n",
|
|
|
+ hose->pci_io_size, size_page);
|
|
|
+
|
|
|
+ /* Establish the mapping */
|
|
|
+ if (__ioremap_at(phys_page, area->addr, size_page,
|
|
|
+ _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ /* Fixup hose IO resource */
|
|
|
+ io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
|
|
|
+ hose->io_resource.start += io_virt_offset;
|
|
|
+ hose->io_resource.end += io_virt_offset;
|
|
|
+
|
|
|
+ DBG(" hose->io_resource=0x%016lx...0x%016lx\n",
|
|
|
+ hose->io_resource.start, hose->io_resource.end);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
-EXPORT_SYMBOL(remap_bus_range);
|
|
|
-
|
|
|
-static void phbs_remap_io(void)
|
|
|
-{
|
|
|
- struct pci_controller *hose, *tmp;
|
|
|
-
|
|
|
- list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
|
|
|
- remap_bus_range(hose->bus);
|
|
|
-}
|
|
|
+EXPORT_SYMBOL_GPL(pcibios_map_io_space);
|
|
|
|
|
|
static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
|
|
|
{
|
|
@@ -1201,8 +1085,7 @@ static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
|
|
|
unsigned long offset;
|
|
|
|
|
|
if (res->flags & IORESOURCE_IO) {
|
|
|
- offset = (unsigned long)hose->io_base_virt - pci_io_base;
|
|
|
-
|
|
|
+ offset = (unsigned long)hose->io_base_virt - _IO_BASE;
|
|
|
res->start += offset;
|
|
|
res->end += offset;
|
|
|
} else if (res->flags & IORESOURCE_MEM) {
|
|
@@ -1217,9 +1100,20 @@ void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
|
|
|
/* Update device resources. */
|
|
|
int i;
|
|
|
|
|
|
- for (i = 0; i < PCI_NUM_RESOURCES; i++)
|
|
|
- if (dev->resource[i].flags)
|
|
|
- fixup_resource(&dev->resource[i], dev);
|
|
|
+ DBG("%s: Fixup resources:\n", pci_name(dev));
|
|
|
+ for (i = 0; i < PCI_NUM_RESOURCES; i++) {
|
|
|
+ struct resource *res = &dev->resource[i];
|
|
|
+ if (!res->flags)
|
|
|
+ continue;
|
|
|
+
|
|
|
+ DBG(" 0x%02x < %08lx:0x%016lx...0x%016lx\n",
|
|
|
+ i, res->flags, res->start, res->end);
|
|
|
+
|
|
|
+ fixup_resource(res, dev);
|
|
|
+
|
|
|
+ DBG(" > %08lx:0x%016lx...0x%016lx\n",
|
|
|
+ res->flags, res->start, res->end);
|
|
|
+ }
|
|
|
}
|
|
|
EXPORT_SYMBOL(pcibios_fixup_device_resources);
|
|
|
|
|
@@ -1360,7 +1254,7 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
|
|
return;
|
|
|
|
|
|
if (rsrc->flags & IORESOURCE_IO)
|
|
|
- offset = (unsigned long)hose->io_base_virt - pci_io_base;
|
|
|
+ offset = (unsigned long)hose->io_base_virt - _IO_BASE;
|
|
|
|
|
|
/* We pass a fully fixed up address to userland for MMIO instead of
|
|
|
* a BAR value because X is lame and expects to be able to use that
|
|
@@ -1410,7 +1304,7 @@ unsigned long pci_address_to_pio(phys_addr_t address)
|
|
|
if (address >= hose->io_base_phys &&
|
|
|
address < (hose->io_base_phys + hose->pci_io_size)) {
|
|
|
unsigned long base =
|
|
|
- (unsigned long)hose->io_base_virt - pci_io_base;
|
|
|
+ (unsigned long)hose->io_base_virt - _IO_BASE;
|
|
|
return base + (address - hose->io_base_phys);
|
|
|
}
|
|
|
}
|