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@@ -14,8 +14,8 @@
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#define DRV_MODULE_NAME "bnx2"
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#define PFX DRV_MODULE_NAME ": "
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-#define DRV_MODULE_VERSION "1.4.31"
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-#define DRV_MODULE_RELDATE "January 19, 2006"
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+#define DRV_MODULE_VERSION "1.4.38"
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+#define DRV_MODULE_RELDATE "February 10, 2006"
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#define RUN_AT(x) (jiffies + (x))
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@@ -360,6 +360,8 @@ bnx2_netif_start(struct bnx2 *bp)
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static void
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bnx2_free_mem(struct bnx2 *bp)
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{
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+ int i;
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+
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if (bp->stats_blk) {
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pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
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bp->stats_blk, bp->stats_blk_mapping);
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@@ -378,19 +380,23 @@ bnx2_free_mem(struct bnx2 *bp)
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}
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kfree(bp->tx_buf_ring);
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bp->tx_buf_ring = NULL;
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- if (bp->rx_desc_ring) {
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- pci_free_consistent(bp->pdev,
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- sizeof(struct rx_bd) * RX_DESC_CNT,
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- bp->rx_desc_ring, bp->rx_desc_mapping);
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- bp->rx_desc_ring = NULL;
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- }
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- kfree(bp->rx_buf_ring);
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+ for (i = 0; i < bp->rx_max_ring; i++) {
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+ if (bp->rx_desc_ring[i])
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+ pci_free_consistent(bp->pdev,
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+ sizeof(struct rx_bd) * RX_DESC_CNT,
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+ bp->rx_desc_ring[i],
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+ bp->rx_desc_mapping[i]);
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+ bp->rx_desc_ring[i] = NULL;
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+ }
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+ vfree(bp->rx_buf_ring);
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bp->rx_buf_ring = NULL;
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}
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static int
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bnx2_alloc_mem(struct bnx2 *bp)
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{
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+ int i;
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+
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bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
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GFP_KERNEL);
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if (bp->tx_buf_ring == NULL)
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@@ -404,18 +410,23 @@ bnx2_alloc_mem(struct bnx2 *bp)
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if (bp->tx_desc_ring == NULL)
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goto alloc_mem_err;
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- bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
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- GFP_KERNEL);
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+ bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
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+ bp->rx_max_ring);
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if (bp->rx_buf_ring == NULL)
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goto alloc_mem_err;
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- memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
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- bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
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- sizeof(struct rx_bd) *
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- RX_DESC_CNT,
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- &bp->rx_desc_mapping);
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- if (bp->rx_desc_ring == NULL)
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- goto alloc_mem_err;
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+ memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
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+ bp->rx_max_ring);
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+
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+ for (i = 0; i < bp->rx_max_ring; i++) {
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+ bp->rx_desc_ring[i] =
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+ pci_alloc_consistent(bp->pdev,
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+ sizeof(struct rx_bd) * RX_DESC_CNT,
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+ &bp->rx_desc_mapping[i]);
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+ if (bp->rx_desc_ring[i] == NULL)
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+ goto alloc_mem_err;
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+
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+ }
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bp->status_blk = pci_alloc_consistent(bp->pdev,
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sizeof(struct status_block),
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@@ -1520,7 +1531,7 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
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struct sk_buff *skb;
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struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
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dma_addr_t mapping;
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- struct rx_bd *rxbd = &bp->rx_desc_ring[index];
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+ struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
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unsigned long align;
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skb = dev_alloc_skb(bp->rx_buf_size);
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@@ -1656,23 +1667,30 @@ static inline void
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bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
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u16 cons, u16 prod)
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{
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- struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
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- struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
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- struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
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- struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
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+ struct sw_bd *cons_rx_buf, *prod_rx_buf;
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+ struct rx_bd *cons_bd, *prod_bd;
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+
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+ cons_rx_buf = &bp->rx_buf_ring[cons];
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+ prod_rx_buf = &bp->rx_buf_ring[prod];
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pci_dma_sync_single_for_device(bp->pdev,
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pci_unmap_addr(cons_rx_buf, mapping),
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bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
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- prod_rx_buf->skb = cons_rx_buf->skb;
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- pci_unmap_addr_set(prod_rx_buf, mapping,
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- pci_unmap_addr(cons_rx_buf, mapping));
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+ bp->rx_prod_bseq += bp->rx_buf_use_size;
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- memcpy(prod_bd, cons_bd, 8);
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+ prod_rx_buf->skb = skb;
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- bp->rx_prod_bseq += bp->rx_buf_use_size;
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+ if (cons == prod)
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+ return;
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+ pci_unmap_addr_set(prod_rx_buf, mapping,
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+ pci_unmap_addr(cons_rx_buf, mapping));
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+
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+ cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
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+ prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
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+ prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
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+ prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
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}
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static int
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@@ -1699,14 +1717,19 @@ bnx2_rx_int(struct bnx2 *bp, int budget)
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u32 status;
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struct sw_bd *rx_buf;
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struct sk_buff *skb;
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+ dma_addr_t dma_addr;
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sw_ring_cons = RX_RING_IDX(sw_cons);
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sw_ring_prod = RX_RING_IDX(sw_prod);
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rx_buf = &bp->rx_buf_ring[sw_ring_cons];
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skb = rx_buf->skb;
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- pci_dma_sync_single_for_cpu(bp->pdev,
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- pci_unmap_addr(rx_buf, mapping),
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+
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+ rx_buf->skb = NULL;
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+
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+ dma_addr = pci_unmap_addr(rx_buf, mapping);
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+
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+ pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
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bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
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rx_hdr = (struct l2_fhdr *) skb->data;
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@@ -1747,8 +1770,7 @@ bnx2_rx_int(struct bnx2 *bp, int budget)
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skb = new_skb;
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}
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else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
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- pci_unmap_single(bp->pdev,
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- pci_unmap_addr(rx_buf, mapping),
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+ pci_unmap_single(bp->pdev, dma_addr,
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bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
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skb_reserve(skb, bp->rx_offset);
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@@ -1794,8 +1816,6 @@ reuse_rx:
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rx_pkt++;
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next_rx:
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- rx_buf->skb = NULL;
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-
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sw_cons = NEXT_RX_BD(sw_cons);
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sw_prod = NEXT_RX_BD(sw_prod);
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@@ -3340,27 +3360,35 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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bp->hw_rx_cons = 0;
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bp->rx_prod_bseq = 0;
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- rxbd = &bp->rx_desc_ring[0];
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- for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
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- rxbd->rx_bd_len = bp->rx_buf_use_size;
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- rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
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- }
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+ for (i = 0; i < bp->rx_max_ring; i++) {
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+ int j;
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- rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
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- rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
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+ rxbd = &bp->rx_desc_ring[i][0];
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+ for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
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+ rxbd->rx_bd_len = bp->rx_buf_use_size;
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+ rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
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+ }
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+ if (i == (bp->rx_max_ring - 1))
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+ j = 0;
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+ else
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+ j = i + 1;
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+ rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
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+ rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
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+ 0xffffffff;
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+ }
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val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
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val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
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val |= 0x02 << 8;
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CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
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- val = (u64) bp->rx_desc_mapping >> 32;
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+ val = (u64) bp->rx_desc_mapping[0] >> 32;
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CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
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- val = (u64) bp->rx_desc_mapping & 0xffffffff;
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+ val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
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CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
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- for ( ;ring_prod < bp->rx_ring_size; ) {
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+ for (i = 0; i < bp->rx_ring_size; i++) {
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if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
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break;
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}
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@@ -3374,6 +3402,29 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
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}
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+static void
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+bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
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+{
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+ u32 num_rings, max;
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+
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+ bp->rx_ring_size = size;
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+ num_rings = 1;
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+ while (size > MAX_RX_DESC_CNT) {
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+ size -= MAX_RX_DESC_CNT;
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+ num_rings++;
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+ }
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+ /* round to next power of 2 */
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+ max = MAX_RX_RINGS;
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+ while ((max & num_rings) == 0)
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+ max >>= 1;
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+
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+ if (num_rings != max)
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+ max <<= 1;
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+
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+ bp->rx_max_ring = max;
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+ bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
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+}
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+
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static void
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bnx2_free_tx_skbs(struct bnx2 *bp)
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{
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@@ -3419,7 +3470,7 @@ bnx2_free_rx_skbs(struct bnx2 *bp)
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if (bp->rx_buf_ring == NULL)
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return;
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- for (i = 0; i < RX_DESC_CNT; i++) {
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+ for (i = 0; i < bp->rx_max_ring_idx; i++) {
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struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
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struct sk_buff *skb = rx_buf->skb;
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@@ -3506,74 +3557,9 @@ bnx2_test_registers(struct bnx2 *bp)
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{ 0x0c00, 0, 0x00000000, 0x00000001 },
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{ 0x0c04, 0, 0x00000000, 0x03ff0001 },
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{ 0x0c08, 0, 0x0f0ff073, 0x00000000 },
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- { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
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- { 0x0c30, 0, 0x00000000, 0xffffffff },
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- { 0x0c34, 0, 0x00000000, 0xffffffff },
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- { 0x0c38, 0, 0x00000000, 0xffffffff },
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- { 0x0c3c, 0, 0x00000000, 0xffffffff },
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- { 0x0c40, 0, 0x00000000, 0xffffffff },
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- { 0x0c44, 0, 0x00000000, 0xffffffff },
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- { 0x0c48, 0, 0x00000000, 0x0007ffff },
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- { 0x0c4c, 0, 0x00000000, 0xffffffff },
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- { 0x0c50, 0, 0x00000000, 0xffffffff },
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- { 0x0c54, 0, 0x00000000, 0xffffffff },
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- { 0x0c58, 0, 0x00000000, 0xffffffff },
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- { 0x0c5c, 0, 0x00000000, 0xffffffff },
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- { 0x0c60, 0, 0x00000000, 0xffffffff },
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- { 0x0c64, 0, 0x00000000, 0xffffffff },
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- { 0x0c68, 0, 0x00000000, 0xffffffff },
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- { 0x0c6c, 0, 0x00000000, 0xffffffff },
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- { 0x0c70, 0, 0x00000000, 0xffffffff },
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- { 0x0c74, 0, 0x00000000, 0xffffffff },
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- { 0x0c78, 0, 0x00000000, 0xffffffff },
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- { 0x0c7c, 0, 0x00000000, 0xffffffff },
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- { 0x0c80, 0, 0x00000000, 0xffffffff },
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- { 0x0c84, 0, 0x00000000, 0xffffffff },
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- { 0x0c88, 0, 0x00000000, 0xffffffff },
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- { 0x0c8c, 0, 0x00000000, 0xffffffff },
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- { 0x0c90, 0, 0x00000000, 0xffffffff },
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- { 0x0c94, 0, 0x00000000, 0xffffffff },
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- { 0x0c98, 0, 0x00000000, 0xffffffff },
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- { 0x0c9c, 0, 0x00000000, 0xffffffff },
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- { 0x0ca0, 0, 0x00000000, 0xffffffff },
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- { 0x0ca4, 0, 0x00000000, 0xffffffff },
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- { 0x0ca8, 0, 0x00000000, 0x0007ffff },
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- { 0x0cac, 0, 0x00000000, 0xffffffff },
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- { 0x0cb0, 0, 0x00000000, 0xffffffff },
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- { 0x0cb4, 0, 0x00000000, 0xffffffff },
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- { 0x0cb8, 0, 0x00000000, 0xffffffff },
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- { 0x0cbc, 0, 0x00000000, 0xffffffff },
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- { 0x0cc0, 0, 0x00000000, 0xffffffff },
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- { 0x0cc4, 0, 0x00000000, 0xffffffff },
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- { 0x0cc8, 0, 0x00000000, 0xffffffff },
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- { 0x0ccc, 0, 0x00000000, 0xffffffff },
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- { 0x0cd0, 0, 0x00000000, 0xffffffff },
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- { 0x0cd4, 0, 0x00000000, 0xffffffff },
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- { 0x0cd8, 0, 0x00000000, 0xffffffff },
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- { 0x0cdc, 0, 0x00000000, 0xffffffff },
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- { 0x0ce0, 0, 0x00000000, 0xffffffff },
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- { 0x0ce4, 0, 0x00000000, 0xffffffff },
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- { 0x0ce8, 0, 0x00000000, 0xffffffff },
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- { 0x0cec, 0, 0x00000000, 0xffffffff },
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- { 0x0cf0, 0, 0x00000000, 0xffffffff },
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- { 0x0cf4, 0, 0x00000000, 0xffffffff },
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- { 0x0cf8, 0, 0x00000000, 0xffffffff },
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- { 0x0cfc, 0, 0x00000000, 0xffffffff },
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- { 0x0d00, 0, 0x00000000, 0xffffffff },
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- { 0x0d04, 0, 0x00000000, 0xffffffff },
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{ 0x1000, 0, 0x00000000, 0x00000001 },
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{ 0x1004, 0, 0x00000000, 0x000f0001 },
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- { 0x1044, 0, 0x00000000, 0xffc003ff },
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- { 0x1080, 0, 0x00000000, 0x0001ffff },
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- { 0x1084, 0, 0x00000000, 0xffffffff },
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- { 0x1088, 0, 0x00000000, 0xffffffff },
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- { 0x108c, 0, 0x00000000, 0xffffffff },
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- { 0x1090, 0, 0x00000000, 0xffffffff },
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- { 0x1094, 0, 0x00000000, 0xffffffff },
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- { 0x1098, 0, 0x00000000, 0xffffffff },
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- { 0x109c, 0, 0x00000000, 0xffffffff },
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- { 0x10a0, 0, 0x00000000, 0xffffffff },
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{ 0x1408, 0, 0x01c00800, 0x00000000 },
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{ 0x149c, 0, 0x8000ffff, 0x00000000 },
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@@ -3585,111 +3571,9 @@ bnx2_test_registers(struct bnx2 *bp)
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{ 0x14c4, 0, 0x00003fff, 0x00000000 },
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{ 0x14cc, 0, 0x00000000, 0x00000001 },
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{ 0x14d0, 0, 0xffffffff, 0x00000000 },
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- { 0x1500, 0, 0x00000000, 0xffffffff },
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- { 0x1504, 0, 0x00000000, 0xffffffff },
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- { 0x1508, 0, 0x00000000, 0xffffffff },
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- { 0x150c, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1510, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1514, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1518, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x151c, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1520, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1524, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1528, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x152c, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1530, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1534, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1538, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x153c, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1540, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1544, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1548, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x154c, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1550, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1554, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1558, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1600, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1604, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1608, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x160c, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1610, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1614, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1618, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x161c, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1620, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1624, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1628, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x162c, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1630, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1634, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1638, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x163c, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1640, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1644, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1648, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x164c, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1650, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1654, 0, 0x00000000, 0xffffffff },
|
|
|
|
|
|
{ 0x1800, 0, 0x00000000, 0x00000001 },
|
|
|
{ 0x1804, 0, 0x00000000, 0x00000003 },
|
|
|
- { 0x1840, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1844, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1848, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x184c, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1850, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1900, 0, 0x7ffbffff, 0x00000000 },
|
|
|
- { 0x1904, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x190c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1914, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x191c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1924, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x192c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1934, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x193c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1944, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x194c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1954, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x195c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1964, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x196c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1974, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x197c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1980, 0, 0x0700ffff, 0x00000000 },
|
|
|
-
|
|
|
- { 0x1c00, 0, 0x00000000, 0x00000001 },
|
|
|
- { 0x1c04, 0, 0x00000000, 0x00000003 },
|
|
|
- { 0x1c08, 0, 0x0000000f, 0x00000000 },
|
|
|
- { 0x1c40, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1c44, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1c48, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1c4c, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1c50, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
|
|
|
- { 0x1d04, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d0c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d14, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d1c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d24, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d2c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d34, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d3c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d44, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d4c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d54, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d5c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d64, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d6c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d74, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d7c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x1d80, 0, 0x0700ffff, 0x00000000 },
|
|
|
-
|
|
|
- { 0x2004, 0, 0x00000000, 0x0337000f },
|
|
|
- { 0x2008, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x200c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x2010, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x2014, 0, 0x801fff80, 0x00000000 },
|
|
|
- { 0x2018, 0, 0x000003ff, 0x00000000 },
|
|
|
|
|
|
{ 0x2800, 0, 0x00000000, 0x00000001 },
|
|
|
{ 0x2804, 0, 0x00000000, 0x00003f01 },
|
|
@@ -3707,16 +3591,6 @@ bnx2_test_registers(struct bnx2 *bp)
|
|
|
{ 0x2c00, 0, 0x00000000, 0x00000011 },
|
|
|
{ 0x2c04, 0, 0x00000000, 0x00030007 },
|
|
|
|
|
|
- { 0x3000, 0, 0x00000000, 0x00000001 },
|
|
|
- { 0x3004, 0, 0x00000000, 0x007007ff },
|
|
|
- { 0x3008, 0, 0x00000003, 0x00000000 },
|
|
|
- { 0x300c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3010, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3014, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3034, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3038, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3050, 0, 0x00000001, 0x00000000 },
|
|
|
-
|
|
|
{ 0x3c00, 0, 0x00000000, 0x00000001 },
|
|
|
{ 0x3c04, 0, 0x00000000, 0x00070000 },
|
|
|
{ 0x3c08, 0, 0x00007f71, 0x07f00000 },
|
|
@@ -3726,88 +3600,11 @@ bnx2_test_registers(struct bnx2 *bp)
|
|
|
{ 0x3c18, 0, 0x00000000, 0xffffffff },
|
|
|
{ 0x3c1c, 0, 0xfffff000, 0x00000000 },
|
|
|
{ 0x3c20, 0, 0xffffff00, 0x00000000 },
|
|
|
- { 0x3c24, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c28, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c2c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c30, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c34, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c38, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c3c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c40, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c44, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c48, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c4c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c50, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c54, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c58, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c5c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c60, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c64, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c68, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c6c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c70, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x3c74, 0, 0x0000003f, 0x00000000 },
|
|
|
- { 0x3c78, 0, 0x00000000, 0x00000000 },
|
|
|
- { 0x3c7c, 0, 0x00000000, 0x00000000 },
|
|
|
- { 0x3c80, 0, 0x3fffffff, 0x00000000 },
|
|
|
- { 0x3c84, 0, 0x0000003f, 0x00000000 },
|
|
|
- { 0x3c88, 0, 0x00000000, 0xffffffff },
|
|
|
- { 0x3c8c, 0, 0x00000000, 0xffffffff },
|
|
|
-
|
|
|
- { 0x4000, 0, 0x00000000, 0x00000001 },
|
|
|
- { 0x4004, 0, 0x00000000, 0x00030000 },
|
|
|
- { 0x4008, 0, 0x00000ff0, 0x00000000 },
|
|
|
- { 0x400c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x4088, 0, 0x00000000, 0x00070303 },
|
|
|
-
|
|
|
- { 0x4400, 0, 0x00000000, 0x00000001 },
|
|
|
- { 0x4404, 0, 0x00000000, 0x00003f01 },
|
|
|
- { 0x4408, 0, 0x7fff00ff, 0x00000000 },
|
|
|
- { 0x440c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x4410, 0, 0xffff, 0x0000 },
|
|
|
- { 0x4414, 0, 0xffff, 0x0000 },
|
|
|
- { 0x4418, 0, 0xffff, 0x0000 },
|
|
|
- { 0x441c, 0, 0xffff, 0x0000 },
|
|
|
- { 0x4428, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x442c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x4430, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x4434, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x4438, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x443c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x4440, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x4444, 0, 0xffffffff, 0x00000000 },
|
|
|
-
|
|
|
- { 0x4c00, 0, 0x00000000, 0x00000001 },
|
|
|
- { 0x4c04, 0, 0x00000000, 0x0000003f },
|
|
|
- { 0x4c08, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
|
|
|
- { 0x4c10, 0, 0x80003fe0, 0x00000000 },
|
|
|
- { 0x4c14, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x4c44, 0, 0x00000000, 0x9fff9fff },
|
|
|
- { 0x4c48, 0, 0x00000000, 0xb3009fff },
|
|
|
- { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
|
|
|
- { 0x4c50, 0, 0x00000000, 0xffffffff },
|
|
|
|
|
|
{ 0x5004, 0, 0x00000000, 0x0000007f },
|
|
|
{ 0x5008, 0, 0x0f0007ff, 0x00000000 },
|
|
|
{ 0x500c, 0, 0xf800f800, 0x07ff07ff },
|
|
|
|
|
|
- { 0x5400, 0, 0x00000008, 0x00000001 },
|
|
|
- { 0x5404, 0, 0x00000000, 0x0000003f },
|
|
|
- { 0x5408, 0, 0x0000001f, 0x00000000 },
|
|
|
- { 0x540c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x5410, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x5414, 0, 0x0000ffff, 0x00000000 },
|
|
|
- { 0x5418, 0, 0x0000ffff, 0x00000000 },
|
|
|
- { 0x541c, 0, 0x0000ffff, 0x00000000 },
|
|
|
- { 0x5420, 0, 0x0000ffff, 0x00000000 },
|
|
|
- { 0x5428, 0, 0x000000ff, 0x00000000 },
|
|
|
- { 0x542c, 0, 0xff00ffff, 0x00000000 },
|
|
|
- { 0x5430, 0, 0x001fff80, 0x00000000 },
|
|
|
- { 0x5438, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x543c, 0, 0xffffffff, 0x00000000 },
|
|
|
- { 0x5440, 0, 0xf800f800, 0x07ff07ff },
|
|
|
-
|
|
|
{ 0x5c00, 0, 0x00000000, 0x00000001 },
|
|
|
{ 0x5c04, 0, 0x00000000, 0x0003000f },
|
|
|
{ 0x5c08, 0, 0x00000003, 0x00000000 },
|
|
@@ -4794,6 +4591,64 @@ bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
|
|
|
info->fw_version[5] = 0;
|
|
|
}
|
|
|
|
|
|
+#define BNX2_REGDUMP_LEN (32 * 1024)
|
|
|
+
|
|
|
+static int
|
|
|
+bnx2_get_regs_len(struct net_device *dev)
|
|
|
+{
|
|
|
+ return BNX2_REGDUMP_LEN;
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
|
|
|
+{
|
|
|
+ u32 *p = _p, i, offset;
|
|
|
+ u8 *orig_p = _p;
|
|
|
+ struct bnx2 *bp = netdev_priv(dev);
|
|
|
+ u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
|
|
|
+ 0x0800, 0x0880, 0x0c00, 0x0c10,
|
|
|
+ 0x0c30, 0x0d08, 0x1000, 0x101c,
|
|
|
+ 0x1040, 0x1048, 0x1080, 0x10a4,
|
|
|
+ 0x1400, 0x1490, 0x1498, 0x14f0,
|
|
|
+ 0x1500, 0x155c, 0x1580, 0x15dc,
|
|
|
+ 0x1600, 0x1658, 0x1680, 0x16d8,
|
|
|
+ 0x1800, 0x1820, 0x1840, 0x1854,
|
|
|
+ 0x1880, 0x1894, 0x1900, 0x1984,
|
|
|
+ 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
|
|
|
+ 0x1c80, 0x1c94, 0x1d00, 0x1d84,
|
|
|
+ 0x2000, 0x2030, 0x23c0, 0x2400,
|
|
|
+ 0x2800, 0x2820, 0x2830, 0x2850,
|
|
|
+ 0x2b40, 0x2c10, 0x2fc0, 0x3058,
|
|
|
+ 0x3c00, 0x3c94, 0x4000, 0x4010,
|
|
|
+ 0x4080, 0x4090, 0x43c0, 0x4458,
|
|
|
+ 0x4c00, 0x4c18, 0x4c40, 0x4c54,
|
|
|
+ 0x4fc0, 0x5010, 0x53c0, 0x5444,
|
|
|
+ 0x5c00, 0x5c18, 0x5c80, 0x5c90,
|
|
|
+ 0x5fc0, 0x6000, 0x6400, 0x6428,
|
|
|
+ 0x6800, 0x6848, 0x684c, 0x6860,
|
|
|
+ 0x6888, 0x6910, 0x8000 };
|
|
|
+
|
|
|
+ regs->version = 0;
|
|
|
+
|
|
|
+ memset(p, 0, BNX2_REGDUMP_LEN);
|
|
|
+
|
|
|
+ if (!netif_running(bp->dev))
|
|
|
+ return;
|
|
|
+
|
|
|
+ i = 0;
|
|
|
+ offset = reg_boundaries[0];
|
|
|
+ p += offset;
|
|
|
+ while (offset < BNX2_REGDUMP_LEN) {
|
|
|
+ *p++ = REG_RD(bp, offset);
|
|
|
+ offset += 4;
|
|
|
+ if (offset == reg_boundaries[i + 1]) {
|
|
|
+ offset = reg_boundaries[i + 2];
|
|
|
+ p = (u32 *) (orig_p + offset);
|
|
|
+ i += 2;
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
static void
|
|
|
bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
|
|
|
{
|
|
@@ -4979,7 +4834,7 @@ bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
|
|
|
{
|
|
|
struct bnx2 *bp = netdev_priv(dev);
|
|
|
|
|
|
- ering->rx_max_pending = MAX_RX_DESC_CNT;
|
|
|
+ ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
|
|
|
ering->rx_mini_max_pending = 0;
|
|
|
ering->rx_jumbo_max_pending = 0;
|
|
|
|
|
@@ -4996,17 +4851,28 @@ bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
|
|
|
{
|
|
|
struct bnx2 *bp = netdev_priv(dev);
|
|
|
|
|
|
- if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
|
|
|
+ if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
|
|
|
(ering->tx_pending > MAX_TX_DESC_CNT) ||
|
|
|
(ering->tx_pending <= MAX_SKB_FRAGS)) {
|
|
|
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
- bp->rx_ring_size = ering->rx_pending;
|
|
|
+ if (netif_running(bp->dev)) {
|
|
|
+ bnx2_netif_stop(bp);
|
|
|
+ bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
|
|
|
+ bnx2_free_skbs(bp);
|
|
|
+ bnx2_free_mem(bp);
|
|
|
+ }
|
|
|
+
|
|
|
+ bnx2_set_rx_ring_size(bp, ering->rx_pending);
|
|
|
bp->tx_ring_size = ering->tx_pending;
|
|
|
|
|
|
if (netif_running(bp->dev)) {
|
|
|
- bnx2_netif_stop(bp);
|
|
|
+ int rc;
|
|
|
+
|
|
|
+ rc = bnx2_alloc_mem(bp);
|
|
|
+ if (rc)
|
|
|
+ return rc;
|
|
|
bnx2_init_nic(bp);
|
|
|
bnx2_netif_start(bp);
|
|
|
}
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@@ -5360,6 +5226,8 @@ static struct ethtool_ops bnx2_ethtool_ops = {
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.get_settings = bnx2_get_settings,
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.set_settings = bnx2_set_settings,
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.get_drvinfo = bnx2_get_drvinfo,
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+ .get_regs_len = bnx2_get_regs_len,
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+ .get_regs = bnx2_get_regs,
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.get_wol = bnx2_get_wol,
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.set_wol = bnx2_set_wol,
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.nway_reset = bnx2_nway_reset,
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@@ -5678,7 +5546,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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bp->mac_addr[5] = (u8) reg;
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bp->tx_ring_size = MAX_TX_DESC_CNT;
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- bp->rx_ring_size = 100;
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+ bnx2_set_rx_ring_size(bp, 100);
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bp->rx_csum = 1;
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@@ -5897,6 +5765,7 @@ bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
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if (!netif_running(dev))
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return 0;
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+ flush_scheduled_work();
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bnx2_netif_stop(bp);
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netif_device_detach(dev);
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del_timer_sync(&bp->timer);
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