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@@ -299,13 +299,6 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
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},
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};
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-static struct samsung_pwm_variant exynos4_pwm_variant = {
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- .bits = 32,
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- .div_base = 0,
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- .has_tint_cstat = true,
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- .tclk_mask = 0,
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-};
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-
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void exynos4_restart(char mode, const char *cmd)
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{
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__raw_writel(0x1, S5P_SWRESET);
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@@ -451,38 +444,10 @@ static void __init exynos5440_map_io(void)
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iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
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}
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-void __init exynos_set_timer_source(u8 channels)
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-{
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- exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
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- exynos4_pwm_variant.output_mask &= ~channels;
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-}
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-
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void __init exynos_init_time(void)
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{
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- unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
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- EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC,
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- EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC,
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- EXYNOS4_IRQ_TIMER4_VIC,
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- };
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-
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- if (of_have_populated_dt()) {
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- of_clk_init(NULL);
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- clocksource_of_init();
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- } else {
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- /* todo: remove after migrating legacy E4 platforms to dt */
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-#ifdef CONFIG_ARCH_EXYNOS4
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- exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
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- exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
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-#endif
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-#ifdef CONFIG_CLKSRC_SAMSUNG_PWM
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- if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
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- samsung_pwm_clocksource_init(S3C_VA_TIMER,
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- timer_irqs, &exynos4_pwm_variant);
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- else
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-#endif
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- mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0,
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- EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
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- }
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+ of_clk_init(NULL);
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+ clocksource_of_init();
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}
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void __init exynos4_init_irq(void)
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