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@@ -166,6 +166,29 @@ static struct mtd_partition osiris_default_nand_part[] = {
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}
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};
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+static struct mtd_partition osiris_default_nand_part_large[] = {
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+ [0] = {
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+ .name = "Boot Agent",
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+ .size = SZ_128K,
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+ .offset = 0,
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+ },
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+ [1] = {
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+ .name = "/boot",
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+ .size = SZ_4M - SZ_128K,
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+ .offset = SZ_128K,
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+ },
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+ [2] = {
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+ .name = "user1",
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+ .offset = SZ_4M,
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+ .size = SZ_32M - SZ_4M,
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+ },
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+ [3] = {
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+ .name = "user2",
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+ .offset = SZ_32M,
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+ .size = MTDPART_SIZ_FULL,
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+ }
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+};
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+
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/* the Osiris has 3 selectable slots for nand-flash, the two
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* on-board chip areas, as well as the external slot.
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*
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@@ -322,14 +345,23 @@ static void __init osiris_map_io(void)
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s3c24xx_init_clocks(0);
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s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
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+ /* check for the newer revision boards with large page nand */
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+
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+ if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
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+ printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
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+ __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
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+ osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
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+ osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
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+ } else {
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+ /* write-protect line to the NAND */
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+ s3c2410_gpio_setpin(S3C2410_GPA0, 1);
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+ }
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+
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/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
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local_irq_save(flags);
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__raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
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local_irq_restore(flags);
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-
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- /* write-protect line to the NAND */
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- s3c2410_gpio_setpin(S3C2410_GPA0, 1);
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}
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static void __init osiris_init(void)
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