|
@@ -797,7 +797,7 @@ static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
|
|
|
{
|
|
|
struct azx *chip = bus->private_data;
|
|
|
unsigned int addr = azx_command_addr(val);
|
|
|
- unsigned int wp;
|
|
|
+ unsigned int wp, rp;
|
|
|
|
|
|
spin_lock_irq(&chip->reg_lock);
|
|
|
|
|
@@ -806,11 +806,18 @@ static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
|
|
|
if (wp == 0xffff) {
|
|
|
/* something wrong, controller likely turned to D3 */
|
|
|
spin_unlock_irq(&chip->reg_lock);
|
|
|
- return -1;
|
|
|
+ return -EIO;
|
|
|
}
|
|
|
wp++;
|
|
|
wp %= ICH6_MAX_CORB_ENTRIES;
|
|
|
|
|
|
+ rp = azx_readw(chip, CORBRP);
|
|
|
+ if (wp == rp) {
|
|
|
+ /* oops, it's full */
|
|
|
+ spin_unlock_irq(&chip->reg_lock);
|
|
|
+ return -EAGAIN;
|
|
|
+ }
|
|
|
+
|
|
|
chip->rirb.cmds[addr]++;
|
|
|
chip->corb.buf[wp] = cpu_to_le32(val);
|
|
|
azx_writel(chip, CORBWP, wp);
|