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@@ -25,6 +25,8 @@
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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+/* Be able to sleep for atleast 4 seconds (usually more) */
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+#define APPTIMER_MIN_RANGE 4
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/*
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* APP side special timer registers
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@@ -308,8 +310,6 @@ static struct clock_event_device clockevent_u300_1mhz = {
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.name = "GPT1",
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.rating = 300, /* Reasonably fast and accurate clock event */
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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- /* 22 calculated using the algorithm in arch/mips/kernel/time.c */
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- .shift = 22,
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.set_next_event = u300_set_next_event,
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.set_mode = u300_set_mode,
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};
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@@ -342,8 +342,6 @@ static struct clocksource clocksource_u300_1mhz = {
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.rating = 300, /* Reasonably fast and accurate clock source */
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.read = u300_get_cycles,
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.mask = CLOCKSOURCE_MASK(32), /* 32 bits */
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- /* 22 calculated using the algorithm in arch/mips/kernel/time.c */
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- .shift = 22,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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@@ -369,11 +367,13 @@ unsigned long long notrace sched_clock(void)
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static void __init u300_timer_init(void)
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{
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struct clk *clk;
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+ unsigned long rate;
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/* Clock the interrupt controller */
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clk = clk_get_sys("apptimer", NULL);
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BUG_ON(IS_ERR(clk));
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clk_enable(clk);
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+ rate = clk_get_rate(clk);
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/*
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* Disable the "OS" and "DD" timers - these are designed for Symbian!
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@@ -412,15 +412,14 @@ static void __init u300_timer_init(void)
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writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
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U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
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- /* This is a pure microsecond clock source */
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- clocksource_u300_1mhz.mult =
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- clocksource_khz2mult(1000, clocksource_u300_1mhz.shift);
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+ clocksource_calc_mult_shift(&clocksource_u300_1mhz,
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+ rate, APPTIMER_MIN_RANGE);
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if (clocksource_register(&clocksource_u300_1mhz))
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printk(KERN_ERR "timer: failed to initialize clock "
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"source %s\n", clocksource_u300_1mhz.name);
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- clockevent_u300_1mhz.mult =
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- div_sc(1000000, NSEC_PER_SEC, clockevent_u300_1mhz.shift);
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+ clockevents_calc_mult_shift(&clockevent_u300_1mhz,
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+ rate, APPTIMER_MIN_RANGE);
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/* 32bit counter, so 32bits delta is max */
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clockevent_u300_1mhz.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz);
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