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@@ -222,6 +222,32 @@ static unsigned int snd_vt1724_get_gpio_data(struct snd_ice1712 *ice)
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return data;
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return data;
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}
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}
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+/*
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+ * MPU401 accessor
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+ */
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+static unsigned char snd_vt1724_mpu401_read(struct snd_mpu401 *mpu,
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+ unsigned long addr)
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+{
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+ /* fix status bits to the standard position */
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+ /* only RX_EMPTY and TX_FULL are checked */
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+ if (addr == MPU401C(mpu))
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+ return (inb(addr) & 0x0c) << 4;
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+ else
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+ return inb(addr);
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+}
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+
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+static void snd_vt1724_mpu401_write(struct snd_mpu401 *mpu,
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+ unsigned char data, unsigned long addr)
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+{
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+ if (addr == MPU401C(mpu)) {
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+ if (data == MPU401_ENTER_UART)
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+ outb(0x01, addr);
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+ /* what else? */
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+ } else
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+ outb(data, addr);
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+}
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+
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+
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/*
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/*
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* Interrupt handler
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* Interrupt handler
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*/
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*/
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@@ -230,24 +256,53 @@ static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id)
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{
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{
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struct snd_ice1712 *ice = dev_id;
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struct snd_ice1712 *ice = dev_id;
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unsigned char status;
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unsigned char status;
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+ unsigned char status_mask =
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+ VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX | VT1724_IRQ_MTPCM;
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int handled = 0;
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int handled = 0;
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+#ifdef CONFIG_SND_DEBUG
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+ int timeout = 0;
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+#endif
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while (1) {
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while (1) {
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status = inb(ICEREG1724(ice, IRQSTAT));
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status = inb(ICEREG1724(ice, IRQSTAT));
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+ status &= status_mask;
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if (status == 0)
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if (status == 0)
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break;
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break;
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-
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+#ifdef CONFIG_SND_DEBUG
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+ if (++timeout > 10) {
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+ printk(KERN_ERR
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+ "ice1724: Too long irq loop, status = 0x%x\n",
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+ status);
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+ break;
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+ }
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+#endif
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handled = 1;
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handled = 1;
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- /* these should probably be separated at some point,
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- * but as we don't currently have MPU support on the board
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- * I will leave it
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- */
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- if ((status & VT1724_IRQ_MPU_RX)||(status & VT1724_IRQ_MPU_TX)) {
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+ if (status & VT1724_IRQ_MPU_TX) {
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if (ice->rmidi[0])
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if (ice->rmidi[0])
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- snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
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- outb(status & (VT1724_IRQ_MPU_RX|VT1724_IRQ_MPU_TX), ICEREG1724(ice, IRQSTAT));
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- status &= ~(VT1724_IRQ_MPU_RX|VT1724_IRQ_MPU_TX);
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+ snd_mpu401_uart_interrupt_tx(irq,
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+ ice->rmidi[0]->private_data);
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+ else /* disable TX to be sure */
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+ outb(inb(ICEREG1724(ice, IRQMASK)) |
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+ VT1724_IRQ_MPU_TX,
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+ ICEREG1724(ice, IRQMASK));
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+ /* Due to mysterical reasons, MPU_TX is always
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+ * generated (and can't be cleared) when a PCM
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+ * playback is going. So let's ignore at the
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+ * next loop.
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+ */
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+ status_mask &= ~VT1724_IRQ_MPU_TX;
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+ }
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+ if (status & VT1724_IRQ_MPU_RX) {
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+ if (ice->rmidi[0])
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+ snd_mpu401_uart_interrupt(irq,
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+ ice->rmidi[0]->private_data);
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+ else /* disable RX to be sure */
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+ outb(inb(ICEREG1724(ice, IRQMASK)) |
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+ VT1724_IRQ_MPU_RX,
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+ ICEREG1724(ice, IRQMASK));
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}
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}
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+ /* ack MPU irq */
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+ outb(status, ICEREG1724(ice, IRQSTAT));
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if (status & VT1724_IRQ_MTPCM) {
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if (status & VT1724_IRQ_MTPCM) {
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/*
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/*
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* Multi-track PCM
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* Multi-track PCM
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@@ -2236,10 +2291,7 @@ static int __devinit snd_vt1724_create(struct snd_card *card,
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}
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}
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/* unmask used interrupts */
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/* unmask used interrupts */
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- if (! (ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_MPU401))
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- mask = VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX;
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- else
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- mask = 0;
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+ mask = VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX;
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outb(mask, ICEREG1724(ice, IRQMASK));
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outb(mask, ICEREG1724(ice, IRQMASK));
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/* don't handle FIFO overrun/underruns (just yet),
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/* don't handle FIFO overrun/underruns (just yet),
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* since they cause machine lockups
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* since they cause machine lockups
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@@ -2373,14 +2425,29 @@ static int __devinit snd_vt1724_probe(struct pci_dev *pci,
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if (! c->no_mpu401) {
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if (! c->no_mpu401) {
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if (ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_MPU401) {
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if (ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_MPU401) {
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+ struct snd_mpu401 *mpu;
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if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
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if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
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ICEREG1724(ice, MPU_CTRL),
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ICEREG1724(ice, MPU_CTRL),
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- MPU401_INFO_INTEGRATED,
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+ (MPU401_INFO_INTEGRATED |
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+ MPU401_INFO_TX_IRQ),
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ice->irq, 0,
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ice->irq, 0,
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&ice->rmidi[0])) < 0) {
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&ice->rmidi[0])) < 0) {
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snd_card_free(card);
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snd_card_free(card);
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return err;
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return err;
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}
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}
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+ mpu = ice->rmidi[0]->private_data;
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+ mpu->read = snd_vt1724_mpu401_read;
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+ mpu->write = snd_vt1724_mpu401_write;
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+ /* unmask MPU RX/TX irqs */
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+ outb(inb(ICEREG1724(ice, IRQMASK)) &
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+ ~(VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX),
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+ ICEREG1724(ice, IRQMASK));
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+#if 0 /* for testing */
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+ /* set watermarks */
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+ outb(VT1724_MPU_RX_FIFO | 0x1,
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+ ICEREG1724(ice, MPU_FIFO_WM));
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+ outb(0x1, ICEREG1724(ice, MPU_FIFO_WM));
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+#endif
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}
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}
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}
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}
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