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@@ -967,7 +967,9 @@ static void XGIfb_post_setmode(struct xgifb_video_info *xgifb_info)
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filter = -1;
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break;
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}
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- xgifb_reg_or(XGIPART1, XGIfb_CRT2_write_enable, 0x01);
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+ xgifb_reg_or(XGIPART1,
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+ IND_XGI_CRT2_WRITE_ENABLE_315,
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+ 0x01);
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if (xgifb_info->TV_type == TVMODE_NTSC) {
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@@ -1335,7 +1337,7 @@ static int XGIfb_pan_var(struct xgifb_video_info *xgifb_info,
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xgifb_reg_and_or(XGISR, 0x37, 0xDF, (base >> 21) & 0x04);
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if (xgifb_info->disp_state & DISPTYPE_DISP2) {
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- xgifb_reg_or(XGIPART1, XGIfb_CRT2_write_enable, 0x01);
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+ xgifb_reg_or(XGIPART1, IND_XGI_CRT2_WRITE_ENABLE_315, 0x01);
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xgifb_reg_set(XGIPART1, 0x06, (base & 0xFF));
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xgifb_reg_set(XGIPART1, 0x05, ((base >> 8) & 0xFF));
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xgifb_reg_set(XGIPART1, 0x04, ((base >> 16) & 0xFF));
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@@ -2023,23 +2025,18 @@ static int __devinit xgifb_probe(struct pci_dev *pdev,
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xgifb_info->chip = XG21;
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else
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xgifb_info->chip = XG20;
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- XGIfb_CRT2_write_enable = IND_XGI_CRT2_WRITE_ENABLE_315;
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break;
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case PCI_DEVICE_ID_XG_40:
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xgifb_info->chip = XG40;
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- XGIfb_CRT2_write_enable = IND_XGI_CRT2_WRITE_ENABLE_315;
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break;
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case PCI_DEVICE_ID_XG_41:
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xgifb_info->chip = XG41;
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- XGIfb_CRT2_write_enable = IND_XGI_CRT2_WRITE_ENABLE_315;
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break;
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case PCI_DEVICE_ID_XG_42:
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xgifb_info->chip = XG42;
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- XGIfb_CRT2_write_enable = IND_XGI_CRT2_WRITE_ENABLE_315;
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break;
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case PCI_DEVICE_ID_XG_27:
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xgifb_info->chip = XG27;
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- XGIfb_CRT2_write_enable = IND_XGI_CRT2_WRITE_ENABLE_315;
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break;
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default:
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ret = -ENODEV;
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