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@@ -398,7 +398,7 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
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* Reprogramming the DPLL is tricky, it must be done from SRAM.
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* (on 730, bit 13 must always be 1)
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*/
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- if (cpu_is_omap730())
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+ if (cpu_is_omap7xx())
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omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
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else
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omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
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@@ -783,7 +783,7 @@ int __init omap1_clk_init(void)
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cpu_mask |= CK_16XX;
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if (cpu_is_omap1510())
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cpu_mask |= CK_1510;
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- if (cpu_is_omap730())
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+ if (cpu_is_omap7xx())
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cpu_mask |= CK_730;
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if (cpu_is_omap310())
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cpu_mask |= CK_310;
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@@ -800,7 +800,7 @@ int __init omap1_clk_init(void)
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crystal_type = info->system_clock_type;
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}
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-#if defined(CONFIG_ARCH_OMAP730)
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+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
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ck_ref.rate = 13000000;
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#elif defined(CONFIG_ARCH_OMAP16XX)
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if (crystal_type == 2)
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@@ -847,7 +847,7 @@ int __init omap1_clk_init(void)
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printk(KERN_ERR "System frequencies not set. Check your config.\n");
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/* Guess sane values (60MHz) */
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omap_writew(0x2290, DPLL_CTL);
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- omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
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+ omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
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ck_dpll1.rate = 60000000;
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}
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#endif
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@@ -873,7 +873,7 @@ int __init omap1_clk_init(void)
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/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
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/* (on 730, bit 13 must not be cleared) */
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- if (cpu_is_omap730())
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+ if (cpu_is_omap7xx())
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omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
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else
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omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
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