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@@ -3693,6 +3693,53 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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+/*
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+ * 'ssi' class
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+ * synchronous serial interface (multichannel and full-duplex serial if)
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+ */
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+
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+static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
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+ .rev_offs = 0x0000,
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+ .sysc_offs = 0x0010,
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+ .syss_offs = 0x0014,
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+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
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+ SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
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+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
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+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
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+ .sysc_fields = &omap_hwmod_sysc_type1,
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+};
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+
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+static struct omap_hwmod_class omap34xx_ssi_hwmod_class = {
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+ .name = "ssi",
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+ .sysc = &omap34xx_ssi_sysc,
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+};
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+
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+static struct omap_hwmod omap34xx_ssi_hwmod = {
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+ .name = "ssi",
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+ .class = &omap34xx_ssi_hwmod_class,
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+ .clkdm_name = "core_l4_clkdm",
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+ .main_clk = "ssi_ssr_fck",
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+ .prcm = {
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+ .omap2 = {
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+ .prcm_reg_id = 1,
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+ .module_bit = OMAP3430_EN_SSI_SHIFT,
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+ .module_offs = CORE_MOD,
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+ .idlest_reg_id = 1,
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+ .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
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+ },
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+ },
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+};
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+
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+/* L4 CORE -> SSI */
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+static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = {
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+ .master = &omap3xxx_l4_core_hwmod,
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+ .slave = &omap34xx_ssi_hwmod,
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+ .clk = "ssi_ick",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
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&omap3xxx_l3_main__l4_core,
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&omap3xxx_l3_main__l4_per,
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@@ -3818,6 +3865,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
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#ifdef CONFIG_OMAP_IOMMU_IVA2
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&omap3xxx_l3_main__mmu_iva,
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#endif
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+ &omap34xx_l4_core__ssi,
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NULL
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};
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