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@@ -41,6 +41,7 @@
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#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
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#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
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#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
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+#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
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#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
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#ifdef RTL8169_DEBUG
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@@ -70,8 +71,6 @@ static const int multicast_filter_limit = 32;
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#define MAC_ADDR_LEN 6
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#define MAX_READ_REQUEST_SHIFT 12
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-#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
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-#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
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#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
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#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
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#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
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@@ -133,6 +132,7 @@ enum mac_version {
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RTL_GIGA_MAC_VER_31,
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RTL_GIGA_MAC_VER_32,
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RTL_GIGA_MAC_VER_33,
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+ RTL_GIGA_MAC_VER_34,
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RTL_GIGA_MAC_NONE = 0xff,
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};
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@@ -216,7 +216,9 @@ static const struct {
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[RTL_GIGA_MAC_VER_32] =
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_R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
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[RTL_GIGA_MAC_VER_33] =
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- _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2)
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+ _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2),
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+ [RTL_GIGA_MAC_VER_34] =
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+ _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
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};
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#undef _R
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@@ -270,10 +272,20 @@ enum rtl_registers {
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TxPoll = 0x38,
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IntrMask = 0x3c,
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IntrStatus = 0x3e,
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+
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TxConfig = 0x40,
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- RxConfig = 0x44,
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+#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
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+#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
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-#define RTL_RX_CONFIG_MASK 0xff7e1880u
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+ RxConfig = 0x44,
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+#define RX128_INT_EN (1 << 15) /* 8111c and later */
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+#define RX_MULTI_EN (1 << 14) /* 8111c only */
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+#define RXCFG_FIFO_SHIFT 13
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+ /* No threshold before first PCI xfer */
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+#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
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+#define RXCFG_DMA_SHIFT 8
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+ /* Unlimited maximum PCI burst. */
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+#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
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RxMissed = 0x4c,
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Cfg9346 = 0x50,
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@@ -327,12 +339,13 @@ enum rtl8168_8101_registers {
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#define EPHYAR_REG_SHIFT 16
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#define EPHYAR_DATA_MASK 0xffff
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DLLPR = 0xd0,
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-#define PM_SWITCH (1 << 6)
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+#define PFM_EN (1 << 6)
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DBG_REG = 0xd1,
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#define FIX_NAK_1 (1 << 4)
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#define FIX_NAK_2 (1 << 3)
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TWSI = 0xd2,
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MCU = 0xd3,
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+#define NOW_IS_OOB (1 << 7)
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#define EN_NDP (1 << 3)
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#define EN_OOB_RESET (1 << 2)
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EFUSEAR = 0xdc,
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@@ -345,18 +358,22 @@ enum rtl8168_8101_registers {
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};
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enum rtl8168_registers {
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+ LED_FREQ = 0x1a,
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+ EEE_LED = 0x1b,
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ERIDR = 0x70,
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ERIAR = 0x74,
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#define ERIAR_FLAG 0x80000000
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#define ERIAR_WRITE_CMD 0x80000000
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#define ERIAR_READ_CMD 0x00000000
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#define ERIAR_ADDR_BYTE_ALIGN 4
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-#define ERIAR_EXGMAC 0
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-#define ERIAR_MSIX 1
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-#define ERIAR_ASF 2
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#define ERIAR_TYPE_SHIFT 16
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-#define ERIAR_BYTEEN 0x0f
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-#define ERIAR_BYTEEN_SHIFT 12
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+#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
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+#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
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+#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
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+#define ERIAR_MASK_SHIFT 12
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+#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
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+#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
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+#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
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EPHY_RXER_NUM = 0x7c,
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OCPDR = 0xb0, /* OCP GPHY access */
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#define OCPDR_WRITE_CMD 0x80000000
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@@ -371,6 +388,7 @@ enum rtl8168_registers {
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RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
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MISC = 0xf0, /* 8168e only. */
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#define TXPLA_RST (1 << 29)
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+#define PWM_EN (1 << 22)
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};
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enum rtl_register_content {
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@@ -395,6 +413,7 @@ enum rtl_register_content {
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RxCRC = (1 << 19),
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/* ChipCmdBits */
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+ StopReq = 0x80,
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CmdReset = 0x10,
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CmdRxEnb = 0x08,
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CmdTxEnb = 0x04,
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@@ -417,10 +436,6 @@ enum rtl_register_content {
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AcceptMyPhys = 0x02,
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AcceptAllPhys = 0x01,
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- /* RxConfigBits */
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- RxCfgFIFOShift = 13,
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- RxCfgDMAShift = 8,
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-
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/* TxConfigBits */
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TxInterFrameGapShift = 24,
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TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
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@@ -712,9 +727,6 @@ static void rtl8169_down(struct net_device *dev);
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static void rtl8169_rx_clear(struct rtl8169_private *tp);
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static int rtl8169_poll(struct napi_struct *napi, int budget);
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-static const unsigned int rtl8169_rx_config =
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- (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
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-
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static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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@@ -1035,6 +1047,49 @@ static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
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return value;
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}
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+static
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+void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
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+{
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+ unsigned int i;
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+
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+ BUG_ON((addr & 3) || (mask == 0));
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+ RTL_W32(ERIDR, val);
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+ RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
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+
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+ for (i = 0; i < 100; i++) {
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+ if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
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+ break;
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+ udelay(100);
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+ }
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+}
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+
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+static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
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+{
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+ u32 value = ~0x00;
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+ unsigned int i;
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+
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+ RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
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+
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+ for (i = 0; i < 100; i++) {
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+ if (RTL_R32(ERIAR) & ERIAR_FLAG) {
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+ value = RTL_R32(ERIDR);
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+ break;
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+ }
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+ udelay(100);
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+ }
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+
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+ return value;
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+}
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+
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+static void
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+rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
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+{
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+ u32 val;
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+
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+ val = rtl_eri_read(ioaddr, addr, type);
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+ rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
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+}
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+
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static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
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{
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u8 value = 0xff;
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@@ -1060,13 +1115,6 @@ static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
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RTL_W16(IntrStatus, 0xffff);
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}
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-static void rtl8169_asic_down(void __iomem *ioaddr)
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-{
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- RTL_W8(ChipCmd, 0x00);
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- rtl8169_irq_mask_and_ack(ioaddr);
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- RTL_R16(CPlusCmd);
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-}
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-
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static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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@@ -1104,6 +1152,39 @@ static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
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rtl_writephy(tp, MII_BMCR, val & 0xffff);
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}
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+static void rtl_link_chg_patch(struct rtl8169_private *tp)
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+{
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+ void __iomem *ioaddr = tp->mmio_addr;
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+ struct net_device *dev = tp->dev;
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+
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+ if (!netif_running(dev))
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+ return;
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+
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+ if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
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+ if (RTL_R8(PHYstatus) & _1000bpsF) {
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+ rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
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+ 0x00000011, ERIAR_EXGMAC);
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+ rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
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+ 0x00000005, ERIAR_EXGMAC);
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+ } else if (RTL_R8(PHYstatus) & _100bps) {
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+ rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
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+ 0x0000001f, ERIAR_EXGMAC);
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+ rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
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+ 0x00000005, ERIAR_EXGMAC);
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+ } else {
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+ rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
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+ 0x0000001f, ERIAR_EXGMAC);
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+ rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
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+ 0x0000003f, ERIAR_EXGMAC);
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+ }
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+ /* Reset packet filter */
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+ rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
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+ ERIAR_EXGMAC);
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+ rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
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+ ERIAR_EXGMAC);
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+ }
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+}
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+
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static void __rtl8169_check_link_status(struct net_device *dev,
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struct rtl8169_private *tp,
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void __iomem *ioaddr, bool pm)
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@@ -1112,6 +1193,7 @@ static void __rtl8169_check_link_status(struct net_device *dev,
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spin_lock_irqsave(&tp->lock, flags);
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if (tp->link_ok(ioaddr)) {
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+ rtl_link_chg_patch(tp);
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/* This is to cancel a scheduled suspend if there's one. */
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if (pm)
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pm_request_resume(&tp->pci_dev->dev);
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@@ -1640,6 +1722,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
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int mac_version;
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} mac_info[] = {
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/* 8168E family. */
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+ { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
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{ 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
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{ 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
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{ 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
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@@ -2617,7 +2700,7 @@ static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
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rtl_patchphy(tp, 0x0d, 1 << 5);
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}
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-static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
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+static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
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{
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static const struct phy_reg phy_reg_init[] = {
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/* Enable Delay cap */
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@@ -2690,6 +2773,91 @@ static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
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rtl_writephy(tp, 0x0d, 0x0000);
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}
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+static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
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+{
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+ static const struct phy_reg phy_reg_init[] = {
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+ /* Enable Delay cap */
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+ { 0x1f, 0x0004 },
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+ { 0x1f, 0x0007 },
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+ { 0x1e, 0x00ac },
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+ { 0x18, 0x0006 },
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+ { 0x1f, 0x0002 },
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+ { 0x1f, 0x0000 },
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+ { 0x1f, 0x0000 },
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+
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+ /* Channel estimation fine tune */
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+ { 0x1f, 0x0003 },
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+ { 0x09, 0xa20f },
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+ { 0x1f, 0x0000 },
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+ { 0x1f, 0x0000 },
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+
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+ /* Green Setting */
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+ { 0x1f, 0x0005 },
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+ { 0x05, 0x8b5b },
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+ { 0x06, 0x9222 },
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+ { 0x05, 0x8b6d },
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+ { 0x06, 0x8000 },
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+ { 0x05, 0x8b76 },
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+ { 0x06, 0x8000 },
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+ { 0x1f, 0x0000 }
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+ };
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+
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+ rtl_apply_firmware(tp);
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+
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+ rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
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+
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+ /* For 4-corner performance improve */
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+ rtl_writephy(tp, 0x1f, 0x0005);
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+ rtl_writephy(tp, 0x05, 0x8b80);
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+ rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
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+ rtl_writephy(tp, 0x1f, 0x0000);
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+
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+ /* PHY auto speed down */
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+ rtl_writephy(tp, 0x1f, 0x0004);
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+ rtl_writephy(tp, 0x1f, 0x0007);
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+ rtl_writephy(tp, 0x1e, 0x002d);
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+ rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
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+ rtl_writephy(tp, 0x1f, 0x0002);
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+ rtl_writephy(tp, 0x1f, 0x0000);
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+ rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
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+
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+ /* improve 10M EEE waveform */
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+ rtl_writephy(tp, 0x1f, 0x0005);
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+ rtl_writephy(tp, 0x05, 0x8b86);
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+ rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
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+ rtl_writephy(tp, 0x1f, 0x0000);
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+
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+ /* Improve 2-pair detection performance */
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+ rtl_writephy(tp, 0x1f, 0x0005);
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+ rtl_writephy(tp, 0x05, 0x8b85);
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+ rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
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+ rtl_writephy(tp, 0x1f, 0x0000);
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+
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+ /* EEE setting */
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+ rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
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+ ERIAR_EXGMAC);
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+ rtl_writephy(tp, 0x1f, 0x0005);
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+ rtl_writephy(tp, 0x05, 0x8b85);
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+ rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
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+ rtl_writephy(tp, 0x1f, 0x0004);
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+ rtl_writephy(tp, 0x1f, 0x0007);
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+ rtl_writephy(tp, 0x1e, 0x0020);
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+ rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
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+ rtl_writephy(tp, 0x1f, 0x0002);
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+ rtl_writephy(tp, 0x1f, 0x0000);
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+ rtl_writephy(tp, 0x0d, 0x0007);
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+ rtl_writephy(tp, 0x0e, 0x003c);
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+ rtl_writephy(tp, 0x0d, 0x4007);
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+ rtl_writephy(tp, 0x0e, 0x0000);
|
|
|
+ rtl_writephy(tp, 0x0d, 0x0000);
|
|
|
+
|
|
|
+ /* Green feature */
|
|
|
+ rtl_writephy(tp, 0x1f, 0x0003);
|
|
|
+ rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
|
|
|
+ rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
|
|
|
+ rtl_writephy(tp, 0x1f, 0x0000);
|
|
|
+}
|
|
|
+
|
|
|
static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
|
|
|
{
|
|
|
static const struct phy_reg phy_reg_init[] = {
|
|
@@ -2809,7 +2977,10 @@ static void rtl_hw_phy_config(struct net_device *dev)
|
|
|
break;
|
|
|
case RTL_GIGA_MAC_VER_32:
|
|
|
case RTL_GIGA_MAC_VER_33:
|
|
|
- rtl8168e_hw_phy_config(tp);
|
|
|
+ rtl8168e_1_hw_phy_config(tp);
|
|
|
+ break;
|
|
|
+ case RTL_GIGA_MAC_VER_34:
|
|
|
+ rtl8168e_2_hw_phy_config(tp);
|
|
|
break;
|
|
|
|
|
|
default:
|
|
@@ -3219,8 +3390,10 @@ static void r8168_pll_power_down(struct rtl8169_private *tp)
|
|
|
rtl_writephy(tp, 0x1f, 0x0000);
|
|
|
rtl_writephy(tp, MII_BMCR, 0x0000);
|
|
|
|
|
|
- RTL_W32(RxConfig, RTL_R32(RxConfig) |
|
|
|
- AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
|
|
|
+ if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
|
|
|
+ tp->mac_version == RTL_GIGA_MAC_VER_33)
|
|
|
+ RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
|
|
|
+ AcceptMulticast | AcceptMyPhys);
|
|
|
return;
|
|
|
}
|
|
|
|
|
@@ -3315,6 +3488,7 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
|
|
|
case RTL_GIGA_MAC_VER_31:
|
|
|
case RTL_GIGA_MAC_VER_32:
|
|
|
case RTL_GIGA_MAC_VER_33:
|
|
|
+ case RTL_GIGA_MAC_VER_34:
|
|
|
ops->down = r8168_pll_power_down;
|
|
|
ops->up = r8168_pll_power_up;
|
|
|
break;
|
|
@@ -3326,6 +3500,47 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
|
|
|
}
|
|
|
}
|
|
|
|
|
|
+static void rtl_init_rxcfg(struct rtl8169_private *tp)
|
|
|
+{
|
|
|
+ void __iomem *ioaddr = tp->mmio_addr;
|
|
|
+
|
|
|
+ switch (tp->mac_version) {
|
|
|
+ case RTL_GIGA_MAC_VER_01:
|
|
|
+ case RTL_GIGA_MAC_VER_02:
|
|
|
+ case RTL_GIGA_MAC_VER_03:
|
|
|
+ case RTL_GIGA_MAC_VER_04:
|
|
|
+ case RTL_GIGA_MAC_VER_05:
|
|
|
+ case RTL_GIGA_MAC_VER_06:
|
|
|
+ case RTL_GIGA_MAC_VER_10:
|
|
|
+ case RTL_GIGA_MAC_VER_11:
|
|
|
+ case RTL_GIGA_MAC_VER_12:
|
|
|
+ case RTL_GIGA_MAC_VER_13:
|
|
|
+ case RTL_GIGA_MAC_VER_14:
|
|
|
+ case RTL_GIGA_MAC_VER_15:
|
|
|
+ case RTL_GIGA_MAC_VER_16:
|
|
|
+ case RTL_GIGA_MAC_VER_17:
|
|
|
+ RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
|
|
|
+ break;
|
|
|
+ case RTL_GIGA_MAC_VER_18:
|
|
|
+ case RTL_GIGA_MAC_VER_19:
|
|
|
+ case RTL_GIGA_MAC_VER_20:
|
|
|
+ case RTL_GIGA_MAC_VER_21:
|
|
|
+ case RTL_GIGA_MAC_VER_22:
|
|
|
+ case RTL_GIGA_MAC_VER_23:
|
|
|
+ case RTL_GIGA_MAC_VER_24:
|
|
|
+ RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
|
|
|
+{
|
|
|
+ tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
|
|
|
+}
|
|
|
+
|
|
|
static void rtl_hw_reset(struct rtl8169_private *tp)
|
|
|
{
|
|
|
void __iomem *ioaddr = tp->mmio_addr;
|
|
@@ -3338,8 +3553,10 @@ static void rtl_hw_reset(struct rtl8169_private *tp)
|
|
|
for (i = 0; i < 100; i++) {
|
|
|
if ((RTL_R8(ChipCmd) & CmdReset) == 0)
|
|
|
break;
|
|
|
- msleep_interruptible(1);
|
|
|
+ udelay(100);
|
|
|
}
|
|
|
+
|
|
|
+ rtl8169_init_ring_indexes(tp);
|
|
|
}
|
|
|
|
|
|
static int __devinit
|
|
@@ -3446,6 +3663,11 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
if (!pci_is_pcie(pdev))
|
|
|
netif_info(tp, probe, dev, "not PCI Express\n");
|
|
|
|
|
|
+ /* Identify chip attached to board */
|
|
|
+ rtl8169_get_mac_version(tp, dev, cfg->default_ver);
|
|
|
+
|
|
|
+ rtl_init_rxcfg(tp);
|
|
|
+
|
|
|
RTL_W16(IntrMask, 0x0000);
|
|
|
|
|
|
rtl_hw_reset(tp);
|
|
@@ -3454,9 +3676,6 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
|
|
pci_set_master(pdev);
|
|
|
|
|
|
- /* Identify chip attached to board */
|
|
|
- rtl8169_get_mac_version(tp, dev, cfg->default_ver);
|
|
|
-
|
|
|
/*
|
|
|
* Pretend we are using VLANs; This bypasses a nasty bug where
|
|
|
* Interrupts stop flowing on high load on 8110SCd controllers.
|
|
@@ -3721,6 +3940,16 @@ err_pm_runtime_put:
|
|
|
goto out;
|
|
|
}
|
|
|
|
|
|
+static void rtl_rx_close(struct rtl8169_private *tp)
|
|
|
+{
|
|
|
+ void __iomem *ioaddr = tp->mmio_addr;
|
|
|
+ u32 rxcfg = RTL_R32(RxConfig);
|
|
|
+
|
|
|
+ rxcfg &= ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast |
|
|
|
+ AcceptMyPhys | AcceptAllPhys);
|
|
|
+ RTL_W32(RxConfig, rxcfg);
|
|
|
+}
|
|
|
+
|
|
|
static void rtl8169_hw_reset(struct rtl8169_private *tp)
|
|
|
{
|
|
|
void __iomem *ioaddr = tp->mmio_addr;
|
|
@@ -3728,28 +3957,27 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
|
|
|
/* Disable interrupts */
|
|
|
rtl8169_irq_mask_and_ack(ioaddr);
|
|
|
|
|
|
+ rtl_rx_close(tp);
|
|
|
+
|
|
|
if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
|
|
|
tp->mac_version == RTL_GIGA_MAC_VER_28 ||
|
|
|
tp->mac_version == RTL_GIGA_MAC_VER_31) {
|
|
|
while (RTL_R8(TxPoll) & NPQ)
|
|
|
udelay(20);
|
|
|
-
|
|
|
+ } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
|
|
|
+ while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
|
|
|
+ udelay(100);
|
|
|
+ } else {
|
|
|
+ RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
|
|
|
+ udelay(100);
|
|
|
}
|
|
|
|
|
|
- /* Reset the chipset */
|
|
|
- RTL_W8(ChipCmd, CmdReset);
|
|
|
-
|
|
|
- /* PCI commit */
|
|
|
- RTL_R8(ChipCmd);
|
|
|
+ rtl_hw_reset(tp);
|
|
|
}
|
|
|
|
|
|
static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
|
|
|
{
|
|
|
void __iomem *ioaddr = tp->mmio_addr;
|
|
|
- u32 cfg = rtl8169_rx_config;
|
|
|
-
|
|
|
- cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
|
|
|
- RTL_W32(RxConfig, cfg);
|
|
|
|
|
|
/* Set DMA burst size and Interframe Gap Time */
|
|
|
RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
|
|
@@ -3760,8 +3988,6 @@ static void rtl_hw_start(struct net_device *dev)
|
|
|
{
|
|
|
struct rtl8169_private *tp = netdev_priv(dev);
|
|
|
|
|
|
- rtl_hw_reset(tp);
|
|
|
-
|
|
|
tp->hw_start(dev);
|
|
|
|
|
|
netif_start_queue(dev);
|
|
@@ -3839,6 +4065,8 @@ static void rtl_hw_start_8169(struct net_device *dev)
|
|
|
tp->mac_version == RTL_GIGA_MAC_VER_04)
|
|
|
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
|
|
|
|
|
|
+ rtl_init_rxcfg(tp);
|
|
|
+
|
|
|
RTL_W8(EarlyTxThres, NoEarlyTx);
|
|
|
|
|
|
rtl_set_rx_max_size(ioaddr, rx_buf_sz);
|
|
@@ -4148,9 +4376,9 @@ static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
|
|
|
rtl_enable_clock_request(pdev);
|
|
|
}
|
|
|
|
|
|
-static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
|
|
|
+static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
|
|
|
{
|
|
|
- static const struct ephy_info e_info_8168e[] = {
|
|
|
+ static const struct ephy_info e_info_8168e_1[] = {
|
|
|
{ 0x00, 0x0200, 0x0100 },
|
|
|
{ 0x00, 0x0000, 0x0004 },
|
|
|
{ 0x06, 0x0002, 0x0001 },
|
|
@@ -4168,7 +4396,7 @@ static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
|
|
|
|
|
|
rtl_csi_access_enable_2(ioaddr);
|
|
|
|
|
|
- rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
|
|
|
+ rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
|
|
|
|
|
|
rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
|
|
|
|
|
@@ -4183,6 +4411,44 @@ static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
|
|
|
RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
|
|
|
}
|
|
|
|
|
|
+static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
|
|
|
+{
|
|
|
+ static const struct ephy_info e_info_8168e_2[] = {
|
|
|
+ { 0x09, 0x0000, 0x0080 },
|
|
|
+ { 0x19, 0x0000, 0x0224 }
|
|
|
+ };
|
|
|
+
|
|
|
+ rtl_csi_access_enable_1(ioaddr);
|
|
|
+
|
|
|
+ rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
|
|
|
+
|
|
|
+ rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
|
|
|
+
|
|
|
+ rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
|
|
|
+ rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
|
|
|
+ rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
|
|
|
+ rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
|
|
|
+ rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
|
|
|
+ rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
|
|
|
+ rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
|
|
|
+ rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
|
|
|
+ ERIAR_EXGMAC);
|
|
|
+
|
|
|
+ RTL_W8(MaxTxPacketSize, 0x27);
|
|
|
+
|
|
|
+ rtl_disable_clock_request(pdev);
|
|
|
+
|
|
|
+ RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
|
|
|
+ RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
|
|
|
+
|
|
|
+ /* Adjust EEE LED frequency */
|
|
|
+ RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
|
|
|
+
|
|
|
+ RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
|
|
|
+ RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
|
|
|
+ RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
|
|
|
+}
|
|
|
+
|
|
|
static void rtl_hw_start_8168(struct net_device *dev)
|
|
|
{
|
|
|
struct rtl8169_private *tp = netdev_priv(dev);
|
|
@@ -4271,7 +4537,10 @@ static void rtl_hw_start_8168(struct net_device *dev)
|
|
|
|
|
|
case RTL_GIGA_MAC_VER_32:
|
|
|
case RTL_GIGA_MAC_VER_33:
|
|
|
- rtl_hw_start_8168e(ioaddr, pdev);
|
|
|
+ rtl_hw_start_8168e_1(ioaddr, pdev);
|
|
|
+ break;
|
|
|
+ case RTL_GIGA_MAC_VER_34:
|
|
|
+ rtl_hw_start_8168e_2(ioaddr, pdev);
|
|
|
break;
|
|
|
|
|
|
default:
|
|
@@ -4368,7 +4637,7 @@ static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
|
|
|
RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
|
|
|
|
|
|
RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
|
|
|
- RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
|
|
|
+ RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
|
|
|
|
|
|
rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
|
|
|
}
|
|
@@ -4570,11 +4839,6 @@ err_out:
|
|
|
return -ENOMEM;
|
|
|
}
|
|
|
|
|
|
-static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
|
|
|
-{
|
|
|
- tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
|
|
|
-}
|
|
|
-
|
|
|
static int rtl8169_init_ring(struct net_device *dev)
|
|
|
{
|
|
|
struct rtl8169_private *tp = netdev_priv(dev);
|
|
@@ -4702,7 +4966,7 @@ static void rtl8169_reset_task(struct work_struct *work)
|
|
|
|
|
|
rtl8169_tx_clear(tp);
|
|
|
|
|
|
- rtl8169_init_ring_indexes(tp);
|
|
|
+ rtl8169_hw_reset(tp);
|
|
|
rtl_hw_start(dev);
|
|
|
netif_wake_queue(dev);
|
|
|
rtl8169_check_link_status(dev, tp, tp->mmio_addr);
|
|
@@ -5116,7 +5380,7 @@ static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
|
|
|
* the chip, so just exit the loop.
|
|
|
*/
|
|
|
if (unlikely(!netif_running(dev))) {
|
|
|
- rtl8169_asic_down(ioaddr);
|
|
|
+ rtl8169_hw_reset(tp);
|
|
|
break;
|
|
|
}
|
|
|
|
|
@@ -5239,7 +5503,7 @@ static void rtl8169_down(struct net_device *dev)
|
|
|
|
|
|
spin_lock_irq(&tp->lock);
|
|
|
|
|
|
- rtl8169_asic_down(ioaddr);
|
|
|
+ rtl8169_hw_reset(tp);
|
|
|
/*
|
|
|
* At this point device interrupts can not be enabled in any function,
|
|
|
* as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
|
|
@@ -5322,8 +5586,7 @@ static void rtl_set_rx_mode(struct net_device *dev)
|
|
|
|
|
|
spin_lock_irqsave(&tp->lock, flags);
|
|
|
|
|
|
- tmp = rtl8169_rx_config | rx_mode |
|
|
|
- (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
|
|
|
+ tmp = RTL_R32(RxConfig) | rx_mode;
|
|
|
|
|
|
if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
|
|
|
u32 data = mc_filter[0];
|
|
@@ -5493,13 +5756,16 @@ static void rtl_shutdown(struct pci_dev *pdev)
|
|
|
|
|
|
spin_lock_irq(&tp->lock);
|
|
|
|
|
|
- rtl8169_asic_down(ioaddr);
|
|
|
+ rtl8169_hw_reset(tp);
|
|
|
|
|
|
spin_unlock_irq(&tp->lock);
|
|
|
|
|
|
if (system_state == SYSTEM_POWER_OFF) {
|
|
|
- /* WoL fails with some 8168 when the receiver is disabled. */
|
|
|
- if (tp->features & RTL_FEATURE_WOL) {
|
|
|
+ /* WoL fails with 8168b when the receiver is disabled. */
|
|
|
+ if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
|
|
|
+ tp->mac_version == RTL_GIGA_MAC_VER_12 ||
|
|
|
+ tp->mac_version == RTL_GIGA_MAC_VER_17) &&
|
|
|
+ (tp->features & RTL_FEATURE_WOL)) {
|
|
|
pci_clear_master(pdev);
|
|
|
|
|
|
RTL_W8(ChipCmd, CmdRxEnb);
|