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@@ -137,7 +137,7 @@ static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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- printk(KERN_INFO "%s: parent is %ld\n", __func__, rate);
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+ printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
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if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
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rate /= 2;
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@@ -573,10 +573,10 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
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unsigned int ptr;
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u32 clkdiv0;
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- printk(KERN_INFO "%s: registering clocks\n", __func__);
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+ printk(KERN_DEBUG "%s: registering clocks\n", __func__);
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clkdiv0 = __raw_readl(S3C_CLK_DIV0);
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- printk(KERN_INFO "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
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+ printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
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xtal_clk = clk_get(NULL, "xtal");
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BUG_ON(IS_ERR(xtal_clk));
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@@ -584,7 +584,7 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
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xtal = clk_get_rate(xtal_clk);
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clk_put(xtal_clk);
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- printk(KERN_INFO "%s: xtal is %ld\n", __func__, xtal);
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+ printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
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epll = s3c6400_get_epll(xtal);
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mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
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