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@@ -261,8 +261,6 @@
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#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
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#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
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-/* Constants used to interpret the masked PCI-X bus speed. */
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-
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#define HALF_DUPLEX 1
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#define FULL_DUPLEX 2
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@@ -330,8 +328,6 @@
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#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
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#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
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-/* Transmit Arbitration Count */
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-
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/* SerDes Control */
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#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
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@@ -800,9 +796,6 @@
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#define M88E1000_PSCR_AUTO_X_1000T 0x0040
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/* Auto crossover enabled all speeds */
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#define M88E1000_PSCR_AUTO_X_MODE 0x0060
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-/* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)
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- * 0=Normal 10BASE-T Rx Threshold
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- */
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#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
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/* M88E1000 PHY Specific Status Register */
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