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@@ -2,6 +2,12 @@
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* sdhci-pltfm.c Support for SDHCI platform devices
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* Copyright (c) 2009 Intel Corporation
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*
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+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
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+ * Copyright (c) 2009 MontaVista Software, Inc.
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+ *
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+ * Authors: Xiaobo Xie <X.Xie@freescale.com>
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+ * Anton Vorontsov <avorontsov@ru.mvista.com>
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+ *
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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@@ -23,13 +29,114 @@
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*/
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#include <linux/err.h>
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-
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+#include <linux/of.h>
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+#ifdef CONFIG_PPC
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+#include <asm/machdep.h>
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+#endif
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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static struct sdhci_ops sdhci_pltfm_ops = {
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};
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+#ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
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+/*
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+ * These accessors are designed for big endian hosts doing I/O to
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+ * little endian controllers incorporating a 32-bit hardware byte swapper.
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+ */
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+u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)
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+{
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+ return in_be32(host->ioaddr + reg);
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+}
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+
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+u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)
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+{
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+ return in_be16(host->ioaddr + (reg ^ 0x2));
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+}
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+
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+u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)
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+{
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+ return in_8(host->ioaddr + (reg ^ 0x3));
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+}
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+
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+void sdhci_be32bs_writel(struct sdhci_host *host, u32 val, int reg)
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+{
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+ out_be32(host->ioaddr + reg, val);
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+}
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+
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+void sdhci_be32bs_writew(struct sdhci_host *host, u16 val, int reg)
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+{
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+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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+ int base = reg & ~0x3;
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+ int shift = (reg & 0x2) * 8;
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+
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+ switch (reg) {
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+ case SDHCI_TRANSFER_MODE:
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+ /*
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+ * Postpone this write, we must do it together with a
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+ * command write that is down below.
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+ */
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+ pltfm_host->xfer_mode_shadow = val;
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+ return;
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+ case SDHCI_COMMAND:
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+ sdhci_be32bs_writel(host,
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+ val << 16 | pltfm_host->xfer_mode_shadow,
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+ SDHCI_TRANSFER_MODE);
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+ return;
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+ }
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+ clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
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+}
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+
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+void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
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+{
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+ int base = reg & ~0x3;
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+ int shift = (reg & 0x3) * 8;
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+
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+ clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
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+}
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+#endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */
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+
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+#ifdef CONFIG_OF
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+static bool sdhci_of_wp_inverted(struct device_node *np)
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+{
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+ if (of_get_property(np, "sdhci,wp-inverted", NULL))
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+ return true;
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+
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+ /* Old device trees don't have the wp-inverted property. */
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+#ifdef CONFIG_PPC
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+ return machine_is(mpc837x_rdb) || machine_is(mpc837x_mds);
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+#else
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+ return false;
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+#endif /* CONFIG_PPC */
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+}
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+
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+void sdhci_get_of_property(struct platform_device *pdev)
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+{
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+ struct device_node *np = pdev->dev.of_node;
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+ struct sdhci_host *host = platform_get_drvdata(pdev);
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+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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+ const __be32 *clk;
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+ int size;
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+
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+ if (of_device_is_available(np)) {
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+ if (of_get_property(np, "sdhci,auto-cmd12", NULL))
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+ host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
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+
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+ if (of_get_property(np, "sdhci,1-bit-only", NULL))
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+ host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
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+
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+ if (sdhci_of_wp_inverted(np))
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+ host->quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
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+
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+ clk = of_get_property(np, "clock-frequency", &size);
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+ if (clk && size == sizeof(*clk) && *clk)
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+ pltfm_host->clock = be32_to_cpup(clk);
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+ }
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+}
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+#else
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+void sdhci_get_of_property(struct platform_device *pdev) {}
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+#endif /* CONFIG_OF */
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+
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struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
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struct sdhci_pltfm_data *pdata)
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{
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@@ -117,6 +224,8 @@ int sdhci_pltfm_register(struct platform_device *pdev,
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if (IS_ERR(host))
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return PTR_ERR(host);
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+ sdhci_get_of_property(pdev);
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+
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ret = sdhci_add_host(host);
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if (ret)
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sdhci_pltfm_free(pdev);
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Shawn Guo