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@@ -652,6 +652,11 @@ static void bnx2x_int_enable(struct bnx2x *bp)
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val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
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REG_WR(bp, addr, val);
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+ /*
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+ * Ensure that HC_CONFIG is written before leading/trailing edge config
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+ */
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+ mmiowb();
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+ barrier();
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if (CHIP_IS_E1H(bp)) {
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/* init leading/trailing edge */
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@@ -666,6 +671,9 @@ static void bnx2x_int_enable(struct bnx2x *bp)
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REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
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REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
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}
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+
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+ /* Make sure that interrupts are indeed enabled from here on */
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+ mmiowb();
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}
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static void bnx2x_int_disable(struct bnx2x *bp)
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@@ -739,6 +747,10 @@ static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
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DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
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(*(u32 *)&igu_ack), hc_addr);
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REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
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+
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+ /* Make sure that ACK is written */
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+ mmiowb();
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+ barrier();
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}
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static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
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@@ -2429,9 +2441,14 @@ static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
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bp->spq_prod_idx++;
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}
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+ /* Make sure that BD data is updated before writing the producer */
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+ wmb();
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+
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REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
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bp->spq_prod_idx);
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+ mmiowb();
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+
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spin_unlock_bh(&bp->spq_lock);
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return 0;
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}
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