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@@ -7,6 +7,7 @@
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* Copyright (c) 2007 Andi Kleen (ak@suse.de)
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* Copyright (c) 2007 Eric Biederman (ebiederm@xmission.com)
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* Copyright (c) 2007 Vivek Goyal (vgoyal@in.ibm.com)
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+ * Copyright (c) 2010 Kees Cook (kees.cook@canonical.com)
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*
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* This source code is licensed under the GNU General Public License,
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* Version 2. See the file COPYING for more details.
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@@ -14,18 +15,17 @@
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* This is a common code for verification whether CPU supports
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* long mode and SSE or not. It is not called directly instead this
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* file is included at various places and compiled in that context.
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- * Following are the current usage.
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+ * This file is expected to run in 32bit code. Currently:
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*
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- * This file is included by both 16bit and 32bit code.
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+ * arch/x86/boot/compressed/head_64.S: Boot cpu verification
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+ * arch/x86/kernel/trampoline_64.S: secondary processor verfication
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+ * arch/x86/kernel/head_32.S: processor startup
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*
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- * arch/x86_64/boot/setup.S : Boot cpu verification (16bit)
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- * arch/x86_64/boot/compressed/head.S: Boot cpu verification (32bit)
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- * arch/x86_64/kernel/trampoline.S: secondary processor verfication (16bit)
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- * arch/x86_64/kernel/acpi/wakeup.S:Verfication at resume (16bit)
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- *
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- * verify_cpu, returns the status of cpu check in register %eax.
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+ * verify_cpu, returns the status of longmode and SSE in register %eax.
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* 0: Success 1: Failure
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*
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+ * On Intel, the XD_DISABLE flag will be cleared as a side-effect.
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+ *
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* The caller needs to check for the error code and take the action
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* appropriately. Either display a message or halt.
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*/
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@@ -62,8 +62,41 @@ verify_cpu:
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cmpl $0x444d4163,%ecx
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jnz verify_cpu_noamd
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mov $1,%di # cpu is from AMD
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+ jmp verify_cpu_check
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verify_cpu_noamd:
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+ cmpl $0x756e6547,%ebx # GenuineIntel?
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+ jnz verify_cpu_check
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+ cmpl $0x49656e69,%edx
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+ jnz verify_cpu_check
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+ cmpl $0x6c65746e,%ecx
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+ jnz verify_cpu_check
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+
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+ # only call IA32_MISC_ENABLE when:
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+ # family > 6 || (family == 6 && model >= 0xd)
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+ movl $0x1, %eax # check CPU family and model
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+ cpuid
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+ movl %eax, %ecx
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+
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+ andl $0x0ff00f00, %eax # mask family and extended family
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+ shrl $8, %eax
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+ cmpl $6, %eax
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+ ja verify_cpu_clear_xd # family > 6, ok
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+ jb verify_cpu_check # family < 6, skip
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+
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+ andl $0x000f00f0, %ecx # mask model and extended model
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+ shrl $4, %ecx
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+ cmpl $0xd, %ecx
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+ jb verify_cpu_check # family == 6, model < 0xd, skip
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+
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+verify_cpu_clear_xd:
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+ movl $MSR_IA32_MISC_ENABLE, %ecx
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+ rdmsr
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+ btrl $2, %edx # clear MSR_IA32_MISC_ENABLE_XD_DISABLE
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+ jnc verify_cpu_check # only write MSR if bit was changed
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+ wrmsr
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+
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+verify_cpu_check:
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movl $0x1,%eax # Does the cpu have what it takes
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cpuid
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andl $REQUIRED_MASK0,%edx
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