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@@ -150,21 +150,21 @@ int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
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memset(&flush_cmd, 0, sizeof(flush_cmd));
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if (flush_control & BIT(IWL_RXON_CTX_BSS))
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- flush_cmd.fifo_control = IWL_SCD_VO_MSK | IWL_SCD_VI_MSK |
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+ flush_cmd.queue_control = IWL_SCD_VO_MSK | IWL_SCD_VI_MSK |
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IWL_SCD_BE_MSK | IWL_SCD_BK_MSK |
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IWL_SCD_MGMT_MSK;
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if ((flush_control & BIT(IWL_RXON_CTX_PAN)) &&
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(priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)))
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- flush_cmd.fifo_control |= IWL_PAN_SCD_VO_MSK |
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+ flush_cmd.queue_control |= IWL_PAN_SCD_VO_MSK |
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IWL_PAN_SCD_VI_MSK | IWL_PAN_SCD_BE_MSK |
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IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK |
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IWL_PAN_SCD_MULTICAST_MSK;
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if (priv->eeprom_data->sku & EEPROM_SKU_CAP_11N_ENABLE)
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- flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
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+ flush_cmd.queue_control |= IWL_AGG_TX_QUEUE_MSK;
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- IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
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- flush_cmd.fifo_control);
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+ IWL_DEBUG_INFO(priv, "queue control: 0x%x\n",
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+ flush_cmd.queue_control);
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flush_cmd.flush_control = cpu_to_le16(flush_control);
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return iwl_dvm_send_cmd(priv, &cmd);
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