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@@ -841,53 +841,6 @@ static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
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chained_irq_exit(chip, desc);
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}
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-static void ipu_ack_irq(struct irq_data *d)
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-{
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- struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
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- irq_hw_number_t irq = d->hwirq;
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-
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- ipu_cm_write(ipu, 1 << (irq % 32), IPU_INT_STAT(irq / 32));
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-}
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-
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-static void ipu_unmask_irq(struct irq_data *d)
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-{
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- struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
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- irq_hw_number_t irq = d->hwirq;
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- unsigned long flags;
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- u32 reg;
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-
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- spin_lock_irqsave(&ipu->lock, flags);
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-
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- reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32));
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- reg |= 1 << (irq % 32);
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- ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32));
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-
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- spin_unlock_irqrestore(&ipu->lock, flags);
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-}
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-
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-static void ipu_mask_irq(struct irq_data *d)
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-{
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- struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
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- irq_hw_number_t irq = d->hwirq;
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- unsigned long flags;
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- u32 reg;
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-
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- spin_lock_irqsave(&ipu->lock, flags);
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-
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- reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32));
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- reg &= ~(1 << (irq % 32));
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- ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32));
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-
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- spin_unlock_irqrestore(&ipu->lock, flags);
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-}
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-
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-static struct irq_chip ipu_irq_chip = {
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- .name = "IPU",
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- .irq_ack = ipu_ack_irq,
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- .irq_mask = ipu_mask_irq,
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- .irq_unmask = ipu_unmask_irq,
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-};
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-
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int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
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enum ipu_channel_irq irq_type)
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{
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@@ -983,32 +936,39 @@ err_register:
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return ret;
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}
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-static int ipu_irq_map(struct irq_domain *h, unsigned int irq,
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- irq_hw_number_t hw)
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-{
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- struct ipu_soc *ipu = h->host_data;
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-
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- irq_set_chip_and_handler(irq, &ipu_irq_chip, handle_level_irq);
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- set_irq_flags(irq, IRQF_VALID);
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- irq_set_chip_data(irq, ipu);
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-
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- return 0;
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-}
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-
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-const struct irq_domain_ops ipu_irq_domain_ops = {
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- .map = ipu_irq_map,
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- .xlate = irq_domain_xlate_onecell,
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-};
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static int ipu_irq_init(struct ipu_soc *ipu)
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{
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+ struct irq_chip_generic *gc;
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+ struct irq_chip_type *ct;
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+ int ret, i;
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+
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ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
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- &ipu_irq_domain_ops, ipu);
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+ &irq_generic_chip_ops, ipu);
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if (!ipu->domain) {
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dev_err(ipu->dev, "failed to add irq domain\n");
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return -ENODEV;
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}
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+ ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
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+ handle_level_irq, 0, IRQF_VALID, 0);
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+ if (ret < 0) {
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+ dev_err(ipu->dev, "failed to alloc generic irq chips\n");
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+ irq_domain_remove(ipu->domain);
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+ return ret;
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+ }
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+
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+ for (i = 0; i < IPU_NUM_IRQS; i += 32) {
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+ gc = irq_get_domain_generic_chip(ipu->domain, i);
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+ gc->reg_base = ipu->cm_reg;
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+ ct = gc->chip_types;
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+ ct->chip.irq_ack = irq_gc_ack_set_bit;
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+ ct->chip.irq_mask = irq_gc_mask_clr_bit;
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+ ct->chip.irq_unmask = irq_gc_mask_set_bit;
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+ ct->regs.ack = IPU_INT_STAT(i / 32);
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+ ct->regs.mask = IPU_INT_CTRL(i / 32);
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+ }
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+
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irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
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irq_set_handler_data(ipu->irq_sync, ipu);
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irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
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@@ -1026,6 +986,8 @@ static void ipu_irq_exit(struct ipu_soc *ipu)
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irq_set_chained_handler(ipu->irq_sync, NULL);
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irq_set_handler_data(ipu->irq_sync, NULL);
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+ /* TODO: remove irq_domain_generic_chips */
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+
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for (i = 0; i < IPU_NUM_IRQS; i++) {
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irq = irq_linear_revmap(ipu->domain, i);
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if (irq)
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