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@@ -58,6 +58,26 @@ static struct clksrc_clk clk_mout_mpll = {
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
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};
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+static struct clk *clkset_armclk_list[] = {
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+ [0] = &clk_mout_apll.clk,
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+ [1] = &clk_mout_mpll.clk,
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+};
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+
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+static struct clksrc_sources clkset_armclk = {
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+ .sources = clkset_armclk_list,
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+ .nr_sources = ARRAY_SIZE(clkset_armclk_list),
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+};
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+
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+static struct clksrc_clk clk_armclk = {
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+ .clk = {
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+ .name = "armclk",
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+ .id = -1,
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+ },
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+ .sources = &clkset_armclk,
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+ .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
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+ .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
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+};
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+
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static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
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@@ -328,6 +348,7 @@ static struct clksrc_clk *sysclks[] = {
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&clk_mout_apll,
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&clk_mout_epll,
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&clk_mout_mpll,
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+ &clk_armclk,
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};
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#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
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@@ -376,7 +397,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
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printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
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apll, mpll, epll);
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- armclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_APLL);
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+ armclk = clk_get_rate(&clk_armclk.clk);
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if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX200_MASK)
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hclk200 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
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else
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