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@@ -48,7 +48,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d)
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}
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/**
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- * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register
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+ * irq_gc_mask_set_bit - Mask irq via setting bit in mask register
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* @d: irq_data
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*
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* Chip has a single mask register. Values of this register are cached
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@@ -66,7 +66,7 @@ void irq_gc_mask_set_bit(struct irq_data *d)
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}
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/**
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- * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
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+ * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
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* @d: irq_data
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*
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* Chip has a single mask register. Values of this register are cached
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@@ -130,7 +130,7 @@ void irq_gc_ack_clr_bit(struct irq_data *d)
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}
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/**
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- * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
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+ * irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt
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* @d: irq_data
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*/
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void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
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