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@@ -197,8 +197,6 @@ static const struct s526_board s526_boards[] = {
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}
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};
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-#define ADDR_CHAN_REG(reg, chan) (dev->iobase + (reg) + (chan) * 8)
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-
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/* this structure is for data unique to this hardware driver. If
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several hardware drivers keep similar information in this structure,
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feel free to suggest moving the variable to the struct comedi_device
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@@ -226,8 +224,8 @@ static int s526_gpct_rinsn(struct comedi_device *dev,
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}
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/* Read the low word first */
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for (i = 0; i < insn->n; i++) {
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- datalow = inw(ADDR_CHAN_REG(REG_C0L, counter_channel));
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- datahigh = inw(ADDR_CHAN_REG(REG_C0H, counter_channel));
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+ datalow = inw(dev->iobase + REG_C0L + counter_channel * 8);
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+ datahigh = inw(dev->iobase + REG_C0H + counter_channel * 8);
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data[i] = (int)(datahigh & 0x00FF);
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data[i] = (data[i] << 16) | (datalow & 0xFFFF);
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/* printk("s526 GPCT[%d]: %x(0x%04x, 0x%04x)\n",
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@@ -283,18 +281,18 @@ static int s526_gpct_insn_config(struct comedi_device *dev,
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cmReg.reg.preloadRegSel = 0; /* PR0 */
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cmReg.reg.reserved = 0;
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- outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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+ outw(cmReg.value, dev->iobase + REG_C0M + subdev_channel * 8);
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- outw(0x0001, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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- outw(0x3C68, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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+ outw(0x0001, dev->iobase + REG_C0H + subdev_channel * 8);
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+ outw(0x3C68, dev->iobase + REG_C0L + subdev_channel * 8);
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/* Reset the counter */
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- outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ outw(0x8000, dev->iobase + REG_C0C + subdev_channel * 8);
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/* Load the counter from PR0 */
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- outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ outw(0x4000, dev->iobase + REG_C0C + subdev_channel * 8);
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/* Reset RCAP (fires one-shot) */
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- outw(0x0008, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ outw(0x0008, dev->iobase + REG_C0C + subdev_channel * 8);
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#endif
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@@ -303,14 +301,14 @@ static int s526_gpct_insn_config(struct comedi_device *dev,
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cmReg.value = data[1] & 0xFFFF;
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/* printk("s526: Counter Mode register=%x\n", cmReg.value); */
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- outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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+ outw(cmReg.value, dev->iobase + REG_C0M + subdev_channel * 8);
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/* Reset the counter if it is software preload */
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if (cmReg.reg.autoLoadResetRcap == 0) {
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/* Reset the counter */
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- outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ outw(0x8000, dev->iobase + REG_C0C + subdev_channel * 8);
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/* Load the counter from PR0
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- * outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ * outw(0x4000, dev->iobase + REG_C0C + subdev_channel * 8);
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*/
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}
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#else
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@@ -338,27 +336,27 @@ static int s526_gpct_insn_config(struct comedi_device *dev,
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/* Set Counter Mode Register */
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cmReg.value = (short)(data[1] & 0xFFFF);
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- outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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+ outw(cmReg.value, dev->iobase + REG_C0M + subdev_channel * 8);
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/* Load the pre-load register high word */
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value = (short)((data[2] >> 16) & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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+ outw(value, dev->iobase + REG_C0H + subdev_channel * 8);
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/* Load the pre-load register low word */
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value = (short)(data[2] & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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+ outw(value, dev->iobase + REG_C0L + subdev_channel * 8);
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/* Write the Counter Control Register */
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if (data[3] != 0) {
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value = (short)(data[3] & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ outw(value, dev->iobase + REG_C0C + subdev_channel * 8);
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}
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/* Reset the counter if it is software preload */
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if (cmReg.reg.autoLoadResetRcap == 0) {
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/* Reset the counter */
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- outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ outw(0x8000, dev->iobase + REG_C0C + subdev_channel * 8);
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/* Load the counter from PR0 */
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- outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ outw(0x4000, dev->iobase + REG_C0C + subdev_channel * 8);
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}
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#endif
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break;
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@@ -378,33 +376,33 @@ static int s526_gpct_insn_config(struct comedi_device *dev,
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/* Set Counter Mode Register */
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cmReg.value = (short)(data[1] & 0xFFFF);
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cmReg.reg.preloadRegSel = 0; /* PR0 */
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- outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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+ outw(cmReg.value, dev->iobase + REG_C0M + subdev_channel * 8);
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/* Load the pre-load register 0 high word */
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value = (short)((data[2] >> 16) & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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+ outw(value, dev->iobase + REG_C0H + subdev_channel * 8);
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/* Load the pre-load register 0 low word */
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value = (short)(data[2] & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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+ outw(value, dev->iobase + REG_C0L + subdev_channel * 8);
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/* Set Counter Mode Register */
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cmReg.value = (short)(data[1] & 0xFFFF);
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cmReg.reg.preloadRegSel = 1; /* PR1 */
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- outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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+ outw(cmReg.value, dev->iobase + REG_C0M + subdev_channel * 8);
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/* Load the pre-load register 1 high word */
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value = (short)((data[3] >> 16) & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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+ outw(value, dev->iobase + REG_C0H + subdev_channel * 8);
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/* Load the pre-load register 1 low word */
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value = (short)(data[3] & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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+ outw(value, dev->iobase + REG_C0L + subdev_channel * 8);
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/* Write the Counter Control Register */
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if (data[4] != 0) {
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value = (short)(data[4] & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ outw(value, dev->iobase + REG_C0C + subdev_channel * 8);
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}
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break;
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@@ -423,33 +421,33 @@ static int s526_gpct_insn_config(struct comedi_device *dev,
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/* Set Counter Mode Register */
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cmReg.value = (short)(data[1] & 0xFFFF);
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cmReg.reg.preloadRegSel = 0; /* PR0 */
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- outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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+ outw(cmReg.value, dev->iobase + REG_C0M + subdev_channel * 8);
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/* Load the pre-load register 0 high word */
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value = (short)((data[2] >> 16) & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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+ outw(value, dev->iobase + REG_C0H + subdev_channel * 8);
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/* Load the pre-load register 0 low word */
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value = (short)(data[2] & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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+ outw(value, dev->iobase + REG_C0L + subdev_channel * 8);
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/* Set Counter Mode Register */
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cmReg.value = (short)(data[1] & 0xFFFF);
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cmReg.reg.preloadRegSel = 1; /* PR1 */
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- outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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+ outw(cmReg.value, dev->iobase + REG_C0M + subdev_channel * 8);
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/* Load the pre-load register 1 high word */
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value = (short)((data[3] >> 16) & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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+ outw(value, dev->iobase + REG_C0H + subdev_channel * 8);
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/* Load the pre-load register 1 low word */
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value = (short)(data[3] & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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+ outw(value, dev->iobase + REG_C0L + subdev_channel * 8);
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/* Write the Counter Control Register */
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if (data[4] != 0) {
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value = (short)(data[4] & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ outw(value, dev->iobase + REG_C0C + subdev_channel * 8);
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}
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break;
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@@ -473,22 +471,22 @@ static int s526_gpct_winsn(struct comedi_device *dev,
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printk(KERN_INFO "s526: GPCT_INSN_WRITE on channel %d\n",
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subdev_channel);
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- cmReg.value = inw(ADDR_CHAN_REG(REG_C0M, subdev_channel));
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+ cmReg.value = inw(dev->iobase + REG_C0M + subdev_channel * 8);
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printk(KERN_INFO "s526: Counter Mode Register: %x\n", cmReg.value);
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/* Check what Application of Counter this channel is configured for */
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switch (devpriv->s526_gpct_config[subdev_channel].app) {
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case PositionMeasurement:
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printk(KERN_INFO "S526: INSN_WRITE: PM\n");
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- outw(0xFFFF & ((*data) >> 16), ADDR_CHAN_REG(REG_C0H,
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- subdev_channel));
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- outw(0xFFFF & (*data), ADDR_CHAN_REG(REG_C0L, subdev_channel));
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+ outw(0xFFFF & ((*data) >> 16), dev->iobase + REG_C0H +
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+ subdev_channel * 8);
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+ outw(0xFFFF & (*data), dev->iobase + REG_C0L + subdev_channel * 8);
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break;
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case SinglePulseGeneration:
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printk(KERN_INFO "S526: INSN_WRITE: SPG\n");
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- outw(0xFFFF & ((*data) >> 16), ADDR_CHAN_REG(REG_C0H,
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- subdev_channel));
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- outw(0xFFFF & (*data), ADDR_CHAN_REG(REG_C0L, subdev_channel));
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+ outw(0xFFFF & ((*data) >> 16), dev->iobase + REG_C0H +
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+ subdev_channel * 8);
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+ outw(0xFFFF & (*data), dev->iobase + REG_C0L + subdev_channel * 8);
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break;
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case PulseTrainGeneration:
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@@ -511,9 +509,9 @@ static int s526_gpct_winsn(struct comedi_device *dev,
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}
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value = (short)((*data >> 16) & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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+ outw(value, dev->iobase + REG_C0H + subdev_channel * 8);
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value = (short)(*data & 0xFFFF);
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- outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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+ outw(value, dev->iobase + REG_C0L + subdev_channel * 8);
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break;
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default: /* Impossible */
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printk
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@@ -843,17 +841,17 @@ static int s526_attach(struct comedi_device *dev, struct comedi_devconfig *it)
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cmReg.reg.preloadRegSel = 0; /* PR0 */
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cmReg.reg.reserved = 0;
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- outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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+ outw(cmReg.value, dev->iobase + REG_C0M + subdev_channel * 8);
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- outw(0x0001, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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- outw(0x3C68, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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+ outw(0x0001, dev->iobase + REG_C0H + subdev_channel * 8);
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+ outw(0x3C68, dev->iobase + REG_C0L + subdev_channel * 8);
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/* Reset the counter */
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- outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ outw(0x8000, dev->iobase + REG_C0C + subdev_channel * 8);
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/* Load the counter from PR0 */
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- outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ outw(0x4000, dev->iobase + REG_C0C + subdev_channel * 8);
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/* Reset RCAP (fires one-shot) */
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- outw(0x0008, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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+ outw(0x0008, dev->iobase + REG_C0C + subdev_channel * 8);
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#else
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@@ -872,35 +870,35 @@ static int s526_attach(struct comedi_device *dev, struct comedi_devconfig *it)
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n = 0;
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printk(KERN_INFO "Mode reg=0x%04x, 0x%04lx\n",
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- cmReg.value, ADDR_CHAN_REG(REG_C0M, n));
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- outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, n));
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+ cmReg.value, dev->iobase + REG_C0M + n * 8);
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+ outw(cmReg.value, dev->iobase + REG_C0M + n * 8);
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udelay(1000);
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printk(KERN_INFO "Read back mode reg=0x%04x\n",
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- inw(ADDR_CHAN_REG(REG_C0M, n)));
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+ inw(dev->iobase + REG_C0M + n * 8));
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/* Load the pre-load register high word */
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/* value = (short) (0x55); */
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-/* outw(value, ADDR_CHAN_REG(REG_C0H, n)); */
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+/* outw(value, dev->iobase + REG_C0H + n * 8); */
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/* Load the pre-load register low word */
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/* value = (short)(0xaa55); */
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-/* outw(value, ADDR_CHAN_REG(REG_C0L, n)); */
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+/* outw(value, dev->iobase + REG_C0L + n * 8); */
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/* Write the Counter Control Register */
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-/* outw(value, ADDR_CHAN_REG(REG_C0C, 0)); */
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+/* outw(value, dev->iobase + REG_C0C + 0 * 8); */
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/* Reset the counter if it is software preload */
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if (cmReg.reg.autoLoadResetRcap == 0) {
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/* Reset the counter */
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- outw(0x8000, ADDR_CHAN_REG(REG_C0C, n));
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+ outw(0x8000, dev->iobase + REG_C0C + n * 8);
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/* Load the counter from PR0 */
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- outw(0x4000, ADDR_CHAN_REG(REG_C0C, n));
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+ outw(0x4000, dev->iobase + REG_C0C + n * 8);
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}
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- outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, n));
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+ outw(cmReg.value, dev->iobase + REG_C0M + n * 8);
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udelay(1000);
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printk(KERN_INFO "Read back mode reg=0x%04x\n",
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- inw(ADDR_CHAN_REG(REG_C0M, n)));
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+ inw(dev->iobase + REG_C0M + n * 8));
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#endif
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printk(KERN_INFO "Current registres:\n");
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