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@@ -132,7 +132,7 @@ device_initcall(snirm_setup_devinit);
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* readb/writeb to access them
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*/
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-static DEFINE_SPINLOCK(sni_rm200_i8259A_lock);
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+static DEFINE_RAW_SPINLOCK(sni_rm200_i8259A_lock);
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#define PIC_CMD 0x00
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#define PIC_IMR 0x01
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#define PIC_ISR PIC_CMD
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@@ -161,13 +161,13 @@ static void sni_rm200_disable_8259A_irq(unsigned int irq)
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irq -= RM200_I8259A_IRQ_BASE;
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mask = 1 << irq;
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- spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
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+ raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
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rm200_cached_irq_mask |= mask;
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if (irq & 8)
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writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
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else
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writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
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- spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
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+ raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
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}
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static void sni_rm200_enable_8259A_irq(unsigned int irq)
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@@ -177,13 +177,13 @@ static void sni_rm200_enable_8259A_irq(unsigned int irq)
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irq -= RM200_I8259A_IRQ_BASE;
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mask = ~(1 << irq);
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- spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
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+ raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
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rm200_cached_irq_mask &= mask;
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if (irq & 8)
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writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
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else
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writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
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- spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
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+ raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
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}
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static inline int sni_rm200_i8259A_irq_real(unsigned int irq)
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@@ -216,7 +216,7 @@ void sni_rm200_mask_and_ack_8259A(unsigned int irq)
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irq -= RM200_I8259A_IRQ_BASE;
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irqmask = 1 << irq;
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- spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
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+ raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
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/*
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* Lightweight spurious IRQ detection. We do not want
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* to overdo spurious IRQ handling - it's usually a sign
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@@ -247,7 +247,7 @@ handle_real_irq:
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writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
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writeb(0x60+irq, rm200_pic_master + PIC_CMD);
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}
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- spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
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+ raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
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return;
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spurious_8259A_irq:
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@@ -298,7 +298,7 @@ static inline int sni_rm200_i8259_irq(void)
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{
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int irq;
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- spin_lock(&sni_rm200_i8259A_lock);
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+ raw_spin_lock(&sni_rm200_i8259A_lock);
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/* Perform an interrupt acknowledge cycle on controller 1. */
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writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */
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@@ -325,7 +325,7 @@ static inline int sni_rm200_i8259_irq(void)
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irq = -1;
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}
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- spin_unlock(&sni_rm200_i8259A_lock);
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+ raw_spin_unlock(&sni_rm200_i8259A_lock);
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return likely(irq >= 0) ? irq + RM200_I8259A_IRQ_BASE : irq;
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}
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@@ -334,7 +334,7 @@ void sni_rm200_init_8259A(void)
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{
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unsigned long flags;
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- spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
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+ raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
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writeb(0xff, rm200_pic_master + PIC_IMR);
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writeb(0xff, rm200_pic_slave + PIC_IMR);
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@@ -352,7 +352,7 @@ void sni_rm200_init_8259A(void)
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writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
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writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
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- spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
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+ raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
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}
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/*
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