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@@ -162,4 +162,47 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
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#endif /* PCI */
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+
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+/* Now for the API extensions over the pci_ one */
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+
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+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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+#define dma_is_consistent(d) (1)
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+
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+static inline int
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+dma_get_cache_alignment(void)
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+{
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+ /* no easy way to get cache size on all processors, so return
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+ * the maximum possible, to be safe */
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+ return (1 << INTERNODE_CACHE_SHIFT);
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+}
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+
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+static inline void
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+dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
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+ unsigned long offset, size_t size,
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+ enum dma_data_direction direction)
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+{
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+ /* just sync everything, that's all the pci API can do */
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+ dma_sync_single_for_cpu(dev, dma_handle, offset+size, direction);
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+}
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+
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+static inline void
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+dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
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+ unsigned long offset, size_t size,
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+ enum dma_data_direction direction)
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+{
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+ /* just sync everything, that's all the pci API can do */
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+ dma_sync_single_for_device(dev, dma_handle, offset+size, direction);
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+}
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+
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+static inline void
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+dma_cache_sync(void *vaddr, size_t size,
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+ enum dma_data_direction direction)
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+{
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+ /* could define this in terms of the dma_cache ... operations,
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+ * but if you get this on a platform, you should convert the platform
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+ * to using the generic device DMA API */
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+ BUG();
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+}
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+
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#endif /* _ASM_SPARC64_DMA_MAPPING_H */
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