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@@ -5140,10 +5140,12 @@ void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
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/*
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* beiscsi_quiesce()- Cleanup Driver resources
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* @phba: Instance Priv structure
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+ * @unload_state:i Clean or EEH unload state
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*
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* Free the OS and HW resources held by the driver
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**/
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-static void beiscsi_quiesce(struct beiscsi_hba *phba)
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+static void beiscsi_quiesce(struct beiscsi_hba *phba,
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+ uint32_t unload_state)
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{
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struct hwi_controller *phwi_ctrlr;
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struct hwi_context_memory *phwi_context;
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@@ -5156,28 +5158,37 @@ static void beiscsi_quiesce(struct beiscsi_hba *phba)
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if (phba->msix_enabled) {
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for (i = 0; i <= phba->num_cpus; i++) {
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msix_vec = phba->msix_entries[i].vector;
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+ synchronize_irq(msix_vec);
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free_irq(msix_vec, &phwi_context->be_eq[i]);
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kfree(phba->msi_name[i]);
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}
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} else
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- if (phba->pcidev->irq)
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+ if (phba->pcidev->irq) {
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+ synchronize_irq(phba->pcidev->irq);
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free_irq(phba->pcidev->irq, phba);
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+ }
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pci_disable_msix(phba->pcidev);
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- destroy_workqueue(phba->wq);
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+
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if (blk_iopoll_enabled)
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for (i = 0; i < phba->num_cpus; i++) {
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pbe_eq = &phwi_context->be_eq[i];
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blk_iopoll_disable(&pbe_eq->iopoll);
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}
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- beiscsi_clean_port(phba);
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- beiscsi_free_mem(phba);
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+ if (unload_state == BEISCSI_CLEAN_UNLOAD) {
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+ destroy_workqueue(phba->wq);
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+ beiscsi_clean_port(phba);
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+ beiscsi_free_mem(phba);
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- beiscsi_unmap_pci_function(phba);
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- pci_free_consistent(phba->pcidev,
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- phba->ctrl.mbox_mem_alloced.size,
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- phba->ctrl.mbox_mem_alloced.va,
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- phba->ctrl.mbox_mem_alloced.dma);
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+ beiscsi_unmap_pci_function(phba);
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+ pci_free_consistent(phba->pcidev,
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+ phba->ctrl.mbox_mem_alloced.size,
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+ phba->ctrl.mbox_mem_alloced.va,
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+ phba->ctrl.mbox_mem_alloced.dma);
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+ } else {
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+ hwi_purge_eq(phba);
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+ hwi_cleanup(phba);
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+ }
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cancel_delayed_work_sync(&phba->beiscsi_hw_check_task);
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}
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@@ -5194,11 +5205,13 @@ static void beiscsi_remove(struct pci_dev *pcidev)
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}
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beiscsi_destroy_def_ifaces(phba);
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- beiscsi_quiesce(phba);
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+ beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD);
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iscsi_boot_destroy_kset(phba->boot_kset);
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iscsi_host_remove(phba->shost);
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pci_dev_put(phba->pcidev);
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iscsi_host_free(phba->shost);
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+ pci_disable_pcie_error_reporting(pcidev);
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+ pci_set_drvdata(pcidev, NULL);
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pci_disable_device(pcidev);
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}
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@@ -5213,7 +5226,7 @@ static void beiscsi_shutdown(struct pci_dev *pcidev)
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return;
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}
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- beiscsi_quiesce(phba);
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+ beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD);
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pci_disable_device(pcidev);
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}
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@@ -5251,6 +5264,167 @@ beiscsi_hw_health_check(struct work_struct *work)
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msecs_to_jiffies(1000));
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}
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+
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+static pci_ers_result_t beiscsi_eeh_err_detected(struct pci_dev *pdev,
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+ pci_channel_state_t state)
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+{
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+ struct beiscsi_hba *phba = NULL;
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+
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+ phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
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+ phba->state |= BE_ADAPTER_PCI_ERR;
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+
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+ beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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+ "BM_%d : EEH error detected\n");
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+
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+ beiscsi_quiesce(phba, BEISCSI_EEH_UNLOAD);
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+
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+ if (state == pci_channel_io_perm_failure) {
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+ beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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+ "BM_%d : EEH : State PERM Failure");
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+ return PCI_ERS_RESULT_DISCONNECT;
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+ }
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+
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+ pci_disable_device(pdev);
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+
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+ /* The error could cause the FW to trigger a flash debug dump.
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+ * Resetting the card while flash dump is in progress
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+ * can cause it not to recover; wait for it to finish.
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+ * Wait only for first function as it is needed only once per
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+ * adapter.
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+ **/
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+ if (pdev->devfn == 0)
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+ ssleep(30);
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+
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+ return PCI_ERS_RESULT_NEED_RESET;
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+}
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+
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+static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev)
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+{
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+ struct beiscsi_hba *phba = NULL;
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+ int status = 0;
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+
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+ phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
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+
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+ beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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+ "BM_%d : EEH Reset\n");
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+
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+ status = pci_enable_device(pdev);
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+ if (status)
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+ return PCI_ERS_RESULT_DISCONNECT;
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+
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+ pci_set_master(pdev);
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+ pci_set_power_state(pdev, PCI_D0);
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+ pci_restore_state(pdev);
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+
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+ /* Wait for the CHIP Reset to complete */
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+ status = be_chk_reset_complete(phba);
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+ if (!status) {
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+ beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
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+ "BM_%d : EEH Reset Completed\n");
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+ } else {
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+ beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
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+ "BM_%d : EEH Reset Completion Failure\n");
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+ return PCI_ERS_RESULT_DISCONNECT;
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+ }
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+
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+ pci_cleanup_aer_uncorrect_error_status(pdev);
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+ return PCI_ERS_RESULT_RECOVERED;
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+}
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+
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+static void beiscsi_eeh_resume(struct pci_dev *pdev)
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+{
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+ int ret = 0, i;
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+ struct be_eq_obj *pbe_eq;
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+ struct beiscsi_hba *phba = NULL;
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+ struct hwi_controller *phwi_ctrlr;
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+ struct hwi_context_memory *phwi_context;
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+
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+ phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
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+ pci_save_state(pdev);
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+
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+ if (enable_msix)
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+ find_num_cpus(phba);
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+ else
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+ phba->num_cpus = 1;
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+
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+ if (enable_msix) {
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+ beiscsi_msix_enable(phba);
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+ if (!phba->msix_enabled)
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+ phba->num_cpus = 1;
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+ }
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+
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+ ret = beiscsi_cmd_reset_function(phba);
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+ if (ret) {
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+ beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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+ "BM_%d : Reset Failed\n");
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+ goto ret_err;
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+ }
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+
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+ ret = be_chk_reset_complete(phba);
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+ if (ret) {
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+ beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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+ "BM_%d : Failed to get out of reset.\n");
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+ goto ret_err;
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+ }
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+
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+ beiscsi_get_params(phba);
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+ phba->shost->max_id = phba->params.cxns_per_ctrl;
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+ phba->shost->can_queue = phba->params.ios_per_ctrl;
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+ ret = hwi_init_controller(phba);
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+
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+ for (i = 0; i < MAX_MCC_CMD; i++) {
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+ init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
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+ phba->ctrl.mcc_tag[i] = i + 1;
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+ phba->ctrl.mcc_numtag[i + 1] = 0;
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+ phba->ctrl.mcc_tag_available++;
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+ }
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+
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+ phwi_ctrlr = phba->phwi_ctrlr;
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+ phwi_context = phwi_ctrlr->phwi_ctxt;
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+
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+ if (blk_iopoll_enabled) {
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+ for (i = 0; i < phba->num_cpus; i++) {
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+ pbe_eq = &phwi_context->be_eq[i];
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+ blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
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+ be_iopoll);
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+ blk_iopoll_enable(&pbe_eq->iopoll);
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+ }
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+
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+ i = (phba->msix_enabled) ? i : 0;
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+ /* Work item for MCC handling */
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+ pbe_eq = &phwi_context->be_eq[i];
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+ INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
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+ } else {
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+ if (phba->msix_enabled) {
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+ for (i = 0; i <= phba->num_cpus; i++) {
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+ pbe_eq = &phwi_context->be_eq[i];
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+ INIT_WORK(&pbe_eq->work_cqs,
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+ beiscsi_process_all_cqs);
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+ }
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+ } else {
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+ pbe_eq = &phwi_context->be_eq[0];
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+ INIT_WORK(&pbe_eq->work_cqs,
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+ beiscsi_process_all_cqs);
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+ }
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+ }
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+
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+ ret = beiscsi_init_irqs(phba);
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+ if (ret < 0) {
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+ beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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+ "BM_%d : beiscsi_eeh_resume - "
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+ "Failed to beiscsi_init_irqs\n");
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+ goto ret_err;
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+ }
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+
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+ hwi_enable_intr(phba);
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+ phba->state &= ~BE_ADAPTER_PCI_ERR;
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+
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+ return;
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+ret_err:
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+ beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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+ "BM_%d : AER EEH Resume Failed\n");
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+}
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+
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static int beiscsi_dev_probe(struct pci_dev *pcidev,
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const struct pci_device_id *id)
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{
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@@ -5258,7 +5432,7 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev,
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struct hwi_controller *phwi_ctrlr;
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struct hwi_context_memory *phwi_context;
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struct be_eq_obj *pbe_eq;
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- int ret, i;
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+ int ret = 0, i;
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ret = beiscsi_enable_pci(pcidev);
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if (ret < 0) {
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@@ -5274,6 +5448,15 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev,
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goto disable_pci;
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}
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+ /* Enable EEH reporting */
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+ ret = pci_enable_pcie_error_reporting(pcidev);
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+ if (ret)
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+ beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
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+ "BM_%d : PCIe Error Reporting "
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+ "Enabling Failed\n");
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+
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+ pci_save_state(pcidev);
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+
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/* Initialize Driver configuration Paramters */
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beiscsi_hba_attrs_init(phba);
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@@ -5359,7 +5542,7 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev,
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goto free_port;
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}
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- for (i = 0; i < MAX_MCC_CMD ; i++) {
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+ for (i = 0; i < MAX_MCC_CMD; i++) {
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init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
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phba->ctrl.mcc_tag[i] = i + 1;
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phba->ctrl.mcc_numtag[i + 1] = 0;
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@@ -5463,6 +5646,12 @@ disable_pci:
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return ret;
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}
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+static struct pci_error_handlers beiscsi_eeh_handlers = {
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+ .error_detected = beiscsi_eeh_err_detected,
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+ .slot_reset = beiscsi_eeh_reset,
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+ .resume = beiscsi_eeh_resume,
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+};
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+
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struct iscsi_transport beiscsi_iscsi_transport = {
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.owner = THIS_MODULE,
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.name = DRV_NAME,
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@@ -5501,7 +5690,8 @@ static struct pci_driver beiscsi_pci_driver = {
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.probe = beiscsi_dev_probe,
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.remove = beiscsi_remove,
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.shutdown = beiscsi_shutdown,
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- .id_table = beiscsi_pci_id_table
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+ .id_table = beiscsi_pci_id_table,
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+ .err_handler = &beiscsi_eeh_handlers
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};
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