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@@ -28,7 +28,7 @@
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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-#define ANOMALY_05000119 (1)
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+#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
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@@ -37,8 +37,6 @@
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#define ANOMALY_05000265 (1)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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-#define ANOMALY_05000312 (ANOMALY_BF527)
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/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
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#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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@@ -153,6 +151,8 @@
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#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
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/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
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#define ANOMALY_05000432 (ANOMALY_BF526)
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+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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+#define ANOMALY_05000443 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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@@ -168,6 +168,7 @@
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#define ANOMALY_05000285 (0)
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#define ANOMALY_05000307 (0)
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#define ANOMALY_05000311 (0)
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+#define ANOMALY_05000312 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000363 (0)
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