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@@ -34,31 +34,29 @@ static void imx3_idle(void)
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{
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unsigned long reg = 0;
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- if (!need_resched())
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- __asm__ __volatile__(
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- /* disable I and D cache */
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- "mrc p15, 0, %0, c1, c0, 0\n"
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- "bic %0, %0, #0x00001000\n"
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- "bic %0, %0, #0x00000004\n"
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- "mcr p15, 0, %0, c1, c0, 0\n"
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- /* invalidate I cache */
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- "mov %0, #0\n"
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- "mcr p15, 0, %0, c7, c5, 0\n"
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- /* clear and invalidate D cache */
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- "mov %0, #0\n"
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- "mcr p15, 0, %0, c7, c14, 0\n"
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- /* WFI */
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- "mov %0, #0\n"
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- "mcr p15, 0, %0, c7, c0, 4\n"
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- "nop\n" "nop\n" "nop\n" "nop\n"
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- "nop\n" "nop\n" "nop\n"
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- /* enable I and D cache */
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- "mrc p15, 0, %0, c1, c0, 0\n"
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- "orr %0, %0, #0x00001000\n"
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- "orr %0, %0, #0x00000004\n"
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- "mcr p15, 0, %0, c1, c0, 0\n"
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- : "=r" (reg));
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- local_irq_enable();
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+ __asm__ __volatile__(
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+ /* disable I and D cache */
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+ "mrc p15, 0, %0, c1, c0, 0\n"
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+ "bic %0, %0, #0x00001000\n"
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+ "bic %0, %0, #0x00000004\n"
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+ "mcr p15, 0, %0, c1, c0, 0\n"
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+ /* invalidate I cache */
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+ "mov %0, #0\n"
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+ "mcr p15, 0, %0, c7, c5, 0\n"
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+ /* clear and invalidate D cache */
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+ "mov %0, #0\n"
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+ "mcr p15, 0, %0, c7, c14, 0\n"
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+ /* WFI */
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+ "mov %0, #0\n"
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+ "mcr p15, 0, %0, c7, c0, 4\n"
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+ "nop\n" "nop\n" "nop\n" "nop\n"
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+ "nop\n" "nop\n" "nop\n"
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+ /* enable I and D cache */
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+ "mrc p15, 0, %0, c1, c0, 0\n"
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+ "orr %0, %0, #0x00001000\n"
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+ "orr %0, %0, #0x00000004\n"
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+ "mcr p15, 0, %0, c1, c0, 0\n"
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+ : "=r" (reg));
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}
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static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
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@@ -134,8 +132,8 @@ void __init imx31_init_early(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX31);
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mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
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- pm_idle = imx3_idle;
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imx_ioremap = imx3_ioremap;
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+ arm_pm_idle = imx3_idle;
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}
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void __init mx31_init_irq(void)
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@@ -197,7 +195,7 @@ void __init imx35_init_early(void)
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mxc_set_cpu_type(MXC_CPU_MX35);
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mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
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- pm_idle = imx3_idle;
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+ arm_pm_idle = imx3_idle;
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imx_ioremap = imx3_ioremap;
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}
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