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@@ -386,7 +386,7 @@ static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
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* channel 0 here at least, but channel 1 has to be enabled by
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* firmware or arch code. We still set both to 16 bits mode.
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*/
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-static unsigned int __init init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
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+static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
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{
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u32 val;
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@@ -399,7 +399,7 @@ static unsigned int __init init_chipset_sl82c105(struct pci_dev *dev, const char
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return dev->irq;
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}
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-static void __init init_dma_sl82c105(ide_hwif_t *hwif, unsigned long dma_base)
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+static void __devinit init_dma_sl82c105(ide_hwif_t *hwif, unsigned long dma_base)
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{
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unsigned int rev;
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u8 dma_state;
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@@ -431,7 +431,7 @@ static void __init init_dma_sl82c105(ide_hwif_t *hwif, unsigned long dma_base)
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* Initialise the chip
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*/
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-static void __init init_hwif_sl82c105(ide_hwif_t *hwif)
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+static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = hwif->pci_dev;
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u32 val;
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