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@@ -2371,11 +2371,11 @@ static unsigned int ilk_fbc_wm_max(void)
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return 15;
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}
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-static void ilk_wm_max(struct drm_device *dev,
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- int level,
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- const struct intel_wm_config *config,
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- enum intel_ddb_partitioning ddb_partitioning,
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- struct hsw_wm_maximums *max)
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+static void ilk_compute_wm_maximums(struct drm_device *dev,
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+ int level,
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+ const struct intel_wm_config *config,
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+ enum intel_ddb_partitioning ddb_partitioning,
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+ struct hsw_wm_maximums *max)
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{
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max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
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max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
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@@ -2626,7 +2626,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
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struct hsw_wm_maximums max;
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/* LP0 watermarks always use 1/2 DDB partitioning */
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- ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
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+ ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
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for (level = 0; level <= max_level; level++)
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ilk_compute_wm_level(dev_priv, level, params,
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@@ -2927,12 +2927,12 @@ static void haswell_update_wm(struct drm_crtc *crtc)
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intel_crtc->wm.active = pipe_wm;
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- ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
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+ ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
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ilk_wm_merge(dev, &max, &lp_wm_1_2);
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/* 5/6 split only in single pipe config on IVB+ */
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if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active == 1) {
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- ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
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+ ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
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ilk_wm_merge(dev, &max, &lp_wm_5_6);
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best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
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