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@@ -76,12 +76,13 @@
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# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
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# define SCIF_ONLY
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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-# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
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-# define SCSPTR0 SCPDR0
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+# define PADR 0xA4050120
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+# define PSDR 0xA405013e
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+# define PWDR 0xA4050166
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+# define PSCR 0xA405011E
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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# define SCIF_ONLY
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-# define PORT_PSCR 0xA405011E
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#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
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# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
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# define SCSPTR0 SCPDR0
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@@ -593,13 +594,25 @@ static inline int sci_rxd_in(struct uart_port *port)
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return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
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return 1;
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}
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-#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7366)
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+#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xffe00000)
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return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
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return 1;
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}
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+#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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+static inline int sci_rxd_in(struct uart_port *port)
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+{
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+ if (port->mapbase == 0xffe00000)
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+ return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
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+ if (port->mapbase == 0xffe10000)
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+ return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
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+ if (port->mapbase == 0xffe20000)
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+ return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
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+
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+ return 1;
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+}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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