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@@ -643,7 +643,7 @@ static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
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if (test_bit(hwc->idx, used_mask))
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break;
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- set_bit(hwc->idx, used_mask);
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+ __set_bit(hwc->idx, used_mask);
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if (assign)
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assign[i] = hwc->idx;
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}
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@@ -692,7 +692,7 @@ static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
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if (j == X86_PMC_IDX_MAX)
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break;
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- set_bit(j, used_mask);
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+ __set_bit(j, used_mask);
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if (assign)
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assign[i] = j;
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@@ -842,7 +842,7 @@ void hw_perf_enable(void)
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* clear active_mask and events[] yet it preserves
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* idx
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*/
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- set_bit(hwc->idx, cpuc->active_mask);
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+ __set_bit(hwc->idx, cpuc->active_mask);
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cpuc->events[hwc->idx] = event;
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x86_pmu.enable(event);
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@@ -1057,7 +1057,7 @@ static void x86_pmu_stop(struct perf_event *event)
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* Must be done before we disable, otherwise the nmi handler
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* could reenable again:
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*/
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- clear_bit(idx, cpuc->active_mask);
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+ __clear_bit(idx, cpuc->active_mask);
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x86_pmu.disable(event);
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/*
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