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@@ -30,6 +30,38 @@
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#include "prcm-regs.h"
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#include "prcm-regs.h"
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#include "memory.h"
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#include "memory.h"
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+#define SMS_BASE 0x68008000
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+#define SMS_SYSCONFIG 0x010
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+
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+#define SDRC_BASE 0x68009000
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+#define SDRC_SYSCONFIG 0x010
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+#define SDRC_SYSSTATUS 0x014
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+
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+static const u32 sms_base = IO_ADDRESS(SMS_BASE);
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+static const u32 sdrc_base = IO_ADDRESS(SDRC_BASE);
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+
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+
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+static inline void sms_write_reg(int idx, u32 val)
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+{
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+ __raw_writel(val, sms_base + idx);
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+}
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+
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+static inline u32 sms_read_reg(int idx)
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+{
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+ return __raw_readl(sms_base + idx);
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+}
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+
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+static inline void sdrc_write_reg(int idx, u32 val)
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+{
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+ __raw_writel(val, sdrc_base + idx);
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+}
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+
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+static inline u32 sdrc_read_reg(int idx)
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+{
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+ return __raw_readl(sdrc_base + idx);
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+}
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+
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+
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static struct memory_timings mem_timings;
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static struct memory_timings mem_timings;
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u32 omap2_memory_get_slow_dll_ctrl(void)
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u32 omap2_memory_get_slow_dll_ctrl(void)
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@@ -99,3 +131,19 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
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/* 90 degree phase for anything below 133Mhz + disable DLL filter */
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/* 90 degree phase for anything below 133Mhz + disable DLL filter */
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mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
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mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
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}
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}
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+
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+void __init omap2_init_memory(void)
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+{
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+ u32 l;
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+
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+ l = sms_read_reg(SMS_SYSCONFIG);
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+ l &= ~(0x3 << 3);
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+ l |= (0x2 << 3);
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+ sms_write_reg(SMS_SYSCONFIG, l);
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+
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+ l = sdrc_read_reg(SDRC_SYSCONFIG);
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+ l &= ~(0x3 << 3);
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+ l |= (0x2 << 3);
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+ sdrc_write_reg(SDRC_SYSCONFIG, l);
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+
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+}
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