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@@ -74,16 +74,6 @@
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* PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary
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* number to differentiate different PLLs controlled by the same PMU rev.
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*/
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-/* pllcontrol registers:
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- * ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>,
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- * p1div, p2div, _bypass_sdmod
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- */
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-#define PMU1_PLL0_PLLCTL0 0
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-#define PMU1_PLL0_PLLCTL1 1
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-#define PMU1_PLL0_PLLCTL2 2
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-#define PMU1_PLL0_PLLCTL3 3
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-#define PMU1_PLL0_PLLCTL4 4
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-#define PMU1_PLL0_PLLCTL5 5
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/* pmu XtalFreqRatio */
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#define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
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@@ -108,80 +98,6 @@
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#define RES4313_HT_AVAIL_RSRC 14
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#define RES4313_MACPHY_CLK_AVAIL_RSRC 15
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-void si_pmu_spuravoid_pllupdate(struct si_pub *sih, u8 spuravoid)
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-{
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- u32 tmp = 0;
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- struct si_info *sii = container_of(sih, struct si_info, pub);
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- struct bcma_device *core;
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-
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- /* switch to chipc */
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- core = sii->icbus->drv_cc.core;
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-
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- switch (ai_get_chip_id(sih)) {
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- case BCM43224_CHIP_ID:
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- case BCM43225_CHIP_ID:
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- if (spuravoid == 1) {
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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- PMU1_PLL0_PLLCTL0);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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- 0x11500010);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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- PMU1_PLL0_PLLCTL1);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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- 0x000C0C06);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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- PMU1_PLL0_PLLCTL2);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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- 0x0F600a08);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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- PMU1_PLL0_PLLCTL3);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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- 0x00000000);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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- PMU1_PLL0_PLLCTL4);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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- 0x2001E920);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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- PMU1_PLL0_PLLCTL5);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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- 0x88888815);
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- } else {
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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- PMU1_PLL0_PLLCTL0);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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- 0x11100010);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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- PMU1_PLL0_PLLCTL1);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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- 0x000c0c06);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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- PMU1_PLL0_PLLCTL2);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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- 0x03000a08);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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- PMU1_PLL0_PLLCTL3);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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- 0x00000000);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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- PMU1_PLL0_PLLCTL4);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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- 0x200005c0);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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- PMU1_PLL0_PLLCTL5);
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- bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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- 0x88888815);
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- }
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- tmp = 1 << 10;
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- break;
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-
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- default:
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- /* bail out */
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- return;
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- }
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-
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- bcma_set32(core, CHIPCREGOFFS(pmucontrol), tmp);
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-}
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-
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u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
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{
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uint delay = PMU_MAX_TRANSITION_DLY;
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