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@@ -644,7 +644,8 @@ unsigned char ibm_architecture_vec[] = {
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W(0xfffe0000), W(0x003a0000), /* POWER5/POWER5+ */
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W(0xffff0000), W(0x003e0000), /* POWER6 */
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W(0xffff0000), W(0x003f0000), /* POWER7 */
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- W(0xffff0000), W(0x004b0000), /* POWER8 */
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+ W(0xffff0000), W(0x004b0000), /* POWER8E */
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+ W(0xffff0000), W(0x004d0000), /* POWER8 */
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W(0xffffffff), W(0x0f000004), /* all 2.07-compliant */
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W(0xffffffff), W(0x0f000003), /* all 2.06-compliant */
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W(0xffffffff), W(0x0f000002), /* all 2.05-compliant */
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@@ -706,7 +707,7 @@ unsigned char ibm_architecture_vec[] = {
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* must match by the macro below. Update the definition if
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* the structure layout changes.
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*/
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-#define IBM_ARCH_VEC_NRCORES_OFFSET 117
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+#define IBM_ARCH_VEC_NRCORES_OFFSET 125
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W(NR_CPUS), /* number of cores supported */
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0,
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0,
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