|
@@ -74,8 +74,8 @@
|
|
|
#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
|
|
|
#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
|
|
|
|
|
|
-#define MII_88EC048_PHY_MSCR1_REG 16
|
|
|
-#define MII_88EC048_PHY_MSCR1_PAD_ODD BIT(6)
|
|
|
+#define MII_88E1318S_PHY_MSCR1_REG 16
|
|
|
+#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
|
|
|
|
|
|
#define MII_88E1121_PHY_LED_CTRL 16
|
|
|
#define MII_88E1121_PHY_LED_PAGE 3
|
|
@@ -240,7 +240,7 @@ static int m88e1121_config_aneg(struct phy_device *phydev)
|
|
|
return err;
|
|
|
}
|
|
|
|
|
|
-static int m88ec048_config_aneg(struct phy_device *phydev)
|
|
|
+static int m88e1318_config_aneg(struct phy_device *phydev)
|
|
|
{
|
|
|
int err, oldpage, mscr;
|
|
|
|
|
@@ -251,10 +251,10 @@ static int m88ec048_config_aneg(struct phy_device *phydev)
|
|
|
if (err < 0)
|
|
|
return err;
|
|
|
|
|
|
- mscr = phy_read(phydev, MII_88EC048_PHY_MSCR1_REG);
|
|
|
- mscr |= MII_88EC048_PHY_MSCR1_PAD_ODD;
|
|
|
+ mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
|
|
|
+ mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
|
|
|
|
|
|
- err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
|
|
|
+ err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
|
|
|
if (err < 0)
|
|
|
return err;
|
|
|
|
|
@@ -659,12 +659,12 @@ static struct phy_driver marvell_drivers[] = {
|
|
|
.driver = { .owner = THIS_MODULE },
|
|
|
},
|
|
|
{
|
|
|
- .phy_id = MARVELL_PHY_ID_88EC048,
|
|
|
+ .phy_id = MARVELL_PHY_ID_88E1318S,
|
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
|
- .name = "Marvell 88EC048",
|
|
|
+ .name = "Marvell 88E1318S",
|
|
|
.features = PHY_GBIT_FEATURES,
|
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
|
- .config_aneg = &m88ec048_config_aneg,
|
|
|
+ .config_aneg = &m88e1318_config_aneg,
|
|
|
.read_status = &marvell_read_status,
|
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
|
.config_intr = &marvell_config_intr,
|