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@@ -652,6 +652,15 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
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mov pc, lr
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ENDPROC(__setup_mmu)
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+@ Enable unaligned access on v6, to allow better code generation
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+@ for the decompressor C code:
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+__armv6_mmu_cache_on:
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+ mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
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+ bic r0, r0, #2 @ A (no unaligned access fault)
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+ orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
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+ mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
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+ b __armv4_mmu_cache_on
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+
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__arm926ejs_mmu_cache_on:
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mov r0, #4 @ put dcache in WT mode
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@@ -694,6 +703,9 @@ __armv7_mmu_cache_on:
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bic r0, r0, #1 << 28 @ clear SCTLR.TRE
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orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
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orr r0, r0, #0x003c @ write buffer
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+ bic r0, r0, #2 @ A (no unaligned access fault)
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+ orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
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+ @ (needed for ARM1176)
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#ifdef CONFIG_MMU
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#ifdef CONFIG_CPU_ENDIAN_BE8
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orr r0, r0, #1 << 25 @ big-endian page tables
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@@ -914,7 +926,7 @@ proc_types:
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.word 0x0007b000 @ ARMv6
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.word 0x000ff000
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- W(b) __armv4_mmu_cache_on
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+ W(b) __armv6_mmu_cache_on
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W(b) __armv4_mmu_cache_off
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W(b) __armv6_mmu_cache_flush
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